Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage with reduced capacitor mismatch sensitivity
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Solution Overview
Problem
Conventional single-ended switched-capacitor gain stages face challenges in balancing low power, high resolution, and high speed due to sensitivity to common-mode reference offset, leading to degradations in integral and differential non-linearity, which affects the dynamic performance of analog-to-digital converters.
Innovation Solution
A non-flip-around multiplying-DAC architecture dynamically generates a reference common mode voltage using switched capacitors pre-charged to the same values, reducing sensitivity to capacitor mismatch and offset, and maintaining linearity by equalizing reference loading during residue generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-ended switched-capacitor gain stage is used to simplify circuit structure, then device complexity is reduced, but the circuit becomes extremely sensitive to common-mode reference offset, causing degradation in linearity (INL and DNL)
Solution Approach 1:
The patent applies preliminary action by pre-charging the reference sampling capacitors to the same voltage level before the gain phase. This pre-charging equalizes the initial conditions for both capacitors, preventing the common-mode reference offset from causing linearity degradation. The pre-charge circuit actively sets both capacitors to identical voltage states, which eliminates the sensitivity issue inherent in conventional single-ended architectures.
Solution Approach 2:
The patent changes the voltage parameter of the reference sampling capacitors by dynamically adjusting their pre-charge levels. Instead of using fixed reference voltages, the system modifies the capacitor voltage states based on the input signal range, enabling the circuit to operate correctly across different input conditions while maintaining linearity and reducing sensitivity to common-mode offsets.
2Device complexity
If conventional switched-capacitor gain stages are used, then the circuit can operate with simple structure, but capacitor mismatch has extreme impact on linearity and dynamic performance
Solution Approach 1:
The patent applies preliminary action by pre-charging the reference sampling capacitors to equalize their initial states before the signal processing phase. This pre-charging operation compensates for capacitor mismatch by ensuring both capacitors start from the same voltage level, thereby reducing the impact of manufacturing variations on linearity and dynamic performance.
Solution Approach 2:
The patent implements feedback through the pre-charge circuit that monitors and adjusts the voltage levels on the reference sampling capacitors. This feedback mechanism ensures that both capacitors are charged to identical voltages despite mismatch, actively compensating for manufacturing variations and maintaining high dynamic performance.
3Object-affected harmful factors
If attempts are made to convert single-ended input to differential signal to reduce offset sensitivity, then offset immunity is improved, but additional high-performance circuitry is required, increasing device complexity and cost
Solution Approach 1:
The patent introduces an intermediary pre-charge circuit that mediates between the single-ended input and the switched-capacitor gain stage. This intermediary circuit equalizes the voltage levels on the reference sampling capacitors, effectively eliminating offset sensitivity issues without requiring a full differential conversion architecture. The pre-charge circuit acts as a simple mediator that resolves the offset problem while maintaining circuit simplicity.
Data Source
AI summary
A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.