Clock-Synchronized Time-Encoding Modulator for Low-Power ADCs
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Solution Overview
Problem
Conventional time-encoding modulators used in ADC circuits face high power consumption due to the need for high-frequency VCOs, which is a challenge especially for battery-powered devices requiring continuous operation for voice control and force sensing applications.
Innovation Solution
A time-encoding modulator design that incorporates a hysteretic comparator module synchronized to a clock signal, with a feedback path and loop filter to generate a time-encoded signal, reducing power consumption by synchronizing transitions and introducing quantization error within the modulator loop, allowing for lower clock rates and noise shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional VCO-based time-decoding converter is used to provide acceptable noise performance, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent replaces the conventional VCO-based time-decoding converter with a counter-based time-decoding converter that counts clock cycles. This substitution eliminates the need for a VCO, thereby reducing power consumption while maintaining acceptable noise performance through the counter's ability to accurately measure time intervals using a stable clock signal
Solution Approach 2:
The patent changes the operating parameters of the system by using a counter clocked at a lower frequency than traditional VCOs operate. By adjusting the counting mechanism and using multiple counting modes (single-shot and continuous), the system achieves acceptable noise performance at lower power consumption levels
2Measurement precision
If the VCO operates at high frequency to provide acceptable noise performance, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent substitutes the VCO with a counter-based time-decoding converter that uses a stable clock signal. This replacement allows the system to achieve accurate time measurements without requiring high-frequency operation, as the counter can accurately count clock cycles at lower frequencies while maintaining measurement precision
3Reliability
If continuous operation is implemented for voice control and force sensing applications, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using a counter-based time-decoding converter that can operate in continuous mode with lower power consumption compared to VCO-based systems. The counter can be clocked at lower frequencies and only performs measurements when needed, enabling continuous operation for voice control and force sensing applications while maintaining lower power consumption levels
Solution Approach 2:
The patent replaces the VCO-based continuous operation system with a counter-based system that achieves reliable continuous operation at lower power consumption. The counter's ability to accurately measure time intervals using a stable clock signal enables continuous monitoring for voice and force sensing applications without the high power requirements of VCOs
Data Source
AI summary
This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronized to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronized to the first clock signal (CLK1).