Clock-Synchronized Time-Encoding Modulator With Digital Delay
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Solution Overview
Problem
Existing signal modulators, such as sigma-delta modulators and time-encoding modulators, face challenges in achieving smaller and lower power designs while maintaining accurate signal conversion, particularly in generating pulse-width modulation signals, due to the need for operational amplifiers and precise reference signals.
Innovation Solution
A time-encoding modulator design incorporating a forward signal path with a comparator, filter, and digital delay element within a feedback loop, synchronized to a clock signal, which includes a latching element and a cycle period controller to control the cycle period of the time-encoded signal, allowing for reduced power consumption and compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time-encoding modulators use operational amplifiers and precise reference signal circuitry to achieve accurate signal conversion, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes operational amplifiers and external reference signal generators from the modulator circuit. The reference signal is generated internally by the feedback loop itself, and amplification functions are eliminated by using direct digital synthesis and comparison techniques. This extraction of complex components directly reduces device complexity while maintaining signal conversion accuracy through alternative architectural approaches.
Solution Approach 2:
The modulator generates its own reference signal through the feedback loop mechanism. The output signal is fed back through a delay element and comparator to create the necessary reference waveform internally, eliminating the need for external reference signal circuitry. This self-service approach reduces both device complexity and power consumption while maintaining the precision needed for accurate time-encoding modulation.
2Measurement precision
If conventional time-encoding modulators use operational amplifiers and reference signal circuitry to achieve accurate signal conversion, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent eliminates power-hungry operational amplifiers and external reference signal generators from the circuit. By using digital logic elements and internal feedback-based reference generation, the design significantly reduces power consumption while maintaining signal conversion accuracy through efficient digital comparison and timing mechanisms.
Solution Approach 2:
The modulator generates its own reference signal through the feedback loop, eliminating the need for external power-intensive reference signal circuitry. The internal generation of reference waveforms through feedback and delay elements reduces overall power consumption while maintaining the precision required for accurate time-encoding modulation.
3Measurement precision
If conventional time-encoding modulators are designed for accurate signal conversion, then measurement precision is improved, but the device size increases
Solution Approach 1:
The patent removes bulky operational amplifier circuits and external reference signal generation hardware from the modulator design. By using integrated digital logic elements and internal feedback mechanisms, the physical footprint is significantly reduced while maintaining signal conversion accuracy through compact digital implementation of modulation functions.
Solution Approach 2:
The patent combines multiple functions into integrated circuit elements. The feedback loop simultaneously provides reference signal generation, signal comparison, and timing control functions that would traditionally require separate components. This merging of functions reduces the overall device size while maintaining the precision needed for accurate time-encoding modulation.
Data Source
AI summary
This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronize any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronized to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronized to the first clock signal.