Dynamic-Zoom ADC With Flash Coarse Stage and Passive Fine Modulator

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Solution Overview

Problem

Analog to digital converters (ADCs) in RF devices face challenges in supporting multiple wireless communications standards due to limitations in power consumption, resolution, and bandwidth, particularly in delta-sigma modulators which are prone to non-idealities and parasitic effects, and require high power consumption.

Innovation Solution

A dynamic-zoom ADC circuit incorporating a coarse flash ADC and a fine passive single-bit delta-sigma modulator, where the flash ADC dynamically updates reference voltages using a multi-bit feedback DAC, reducing quantization noise and improving resolution, allowing for lower oversampling ratio values and supporting multiple wireless standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a passive delta-sigma modulator is used to reduce power consumption, then power consumption is reduced, but resolution is limited due to limited options for reducing quantization noise power

Engineering Contradiction:
Improvepower consumptionVSAvoidresolution
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The ADC is divided into two segments: a coarse flash ADC that handles the most significant bits and a fine passive delta-sigma modulator that handles the least significant bits. This segmentation allows each part to be optimized independently - the flash ADC provides coarse conversion with high speed and low power, while the delta-sigma modulator provides fine resolution without requiring power-hungry OTAs, achieving both low power consumption and high resolution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention merges the flash ADC and delta-sigma modulator into a unified hybrid architecture where the flash ADC output feeds into the delta-sigma modulator. This combination allows the system to benefit from both architectures: the flash ADC's speed and low power consumption, and the delta-sigma modulator's noise shaping and high resolution capabilities, thereby resolving the contradiction between power consumption and resolution.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If a multi-mode CT delta-sigma modulator is designed to support multiple communications standards, then adaptability is improved, but device complexity increases due to multiple switchable passive resistor-capacitor combinations

Engineering Contradiction:
Improvemulti-mode operationVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic reconfiguration capability where the flash ADC can be dynamically adjusted in resolution and the delta-sigma modulator can be dynamically reconfigured for different oversampling ratios based on the required communication standard. This dynamic adaptability allows the system to support multiple modes (GSM, UMTS, LTE, WiMAX) without requiring multiple fixed architectures, reducing complexity while maintaining versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operating parameters (flash ADC resolution, delta-sigma modulator oversampling ratio, sampling frequency) to adapt to different communication standards. By varying these parameters rather than changing the fundamental architecture, the system achieves multi-mode operation with reduced complexity compared to having multiple dedicated circuits for each standard.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If the flash ADC updates reference voltages dynamically using feedback DAC, then quantization noise is reduced and resolution is improved, but device complexity increases

Engineering Contradiction:
ImproveresolutionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the flash ADC output is fed back through a DAC to dynamically adjust the reference voltages for the delta-sigma modulator. This feedback loop allows the system to track the input signal range and optimize the quantization process, reducing quantization noise and improving resolution. The feedback architecture is relatively simple compared to the resolution improvements it achieves.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10541706B2Dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator
Publication Date: 2020.01.21 THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIV OF ARIZONA
  • US10541706B2 patent drawing
  • US10541706B2 patent drawing
  • US10541706B2 patent drawing

AI summary

A dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator is disclosed. Radio frequency (RF) devices incorporating aspects of the present disclosure may support multiple wireless modes operating at different frequencies. Therefore, the RF devices have need for an ADC which is flexible and optimizable in terms of resolution, bandwidth, and power consumption. In this regard, the RF devices incorporate circuits, such as ADC circuits, which incorporate a discrete-time passive delta-sigma modulator. In order to improve the resolution of the delta-sigma modulator, a coarse ADC is deployed as a zooming unit to a single-bit passive delta-sigma modulator to provide a coarse digital conversion. Coarse conversion is used to dynamically update reference voltages at an input of the delta-sigma modulator using a multi-bit feedback digital to analog converter (DAC). The dynamic-zoom ADC supports multiple modes with improved power and quantization noise.