Parallel Delta-Sigma Architecture for RF PA Switching-Speed Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power amplifier architectures, such as switch-mode PAs, face limitations in achieving high power conversion efficiency at multi-GHz frequencies due to constraints on switching speed and noise shaping filter design, particularly for RF applications, which are essential for modern communication standards like 5G and WiFi.
Innovation Solution
The implementation of a parallel delta sigma modulator architecture that demultiplexes input signals into multiple streams, processes them using un-constrained delta sigma modulators with noise shaping filters, and multiplexes the outputs into a pulse train, allowing for higher switching speeds and improved power conversion efficiency by reducing peak-to-average power ratio (PAPR) without degrading signal linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switch-mode PAs operate at multi-GHz frequencies, then power conversion efficiency is improved, but switching speed constraints and noise shaping filter design limitations worsen
Solution Approach 1:
The patent divides the single delta-sigma modulator into multiple parallel modulators operating at lower individual frequencies. Each parallel modulator processes a portion of the signal, allowing the system to achieve high overall switching frequency (multi-GHz) while each individual modulator operates at a manageable frequency, thus resolving the switching speed constraint while maintaining high power conversion efficiency
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. By distributing the modulation across multiple parallel paths that can be independently optimized, the system achieves high effective switching frequency without requiring each individual component to operate at multi-GHz speeds, thereby resolving the speed bottleneck
2Speed
If parallel delta sigma modulators are used, then switching speed and power conversion efficiency are improved, but device complexity increases
Solution Approach 1:
The patent segments the complex high-speed modulation task into simpler parallel sub-tasks. Each parallel delta-sigma modulator uses a relaxed, un-constrained noise shaping filter that is simpler to design and implement. The overall system achieves high switching speed through parallel operation rather than through complex high-speed filtering, thus reducing individual component complexity while maintaining high system-level performance
Solution Approach 2:
The patent changes the operational parameters of each parallel modulator to use lower individual switching frequencies and un-constrained noise shaping filters. This parameter change allows each modulator to be simpler in design while the parallel combination achieves the desired high effective switching frequency, thereby reducing device complexity at the component level
3Device complexity
If un-constrained noise shaping filters are used, then design complexity is reduced and switching speed is improved, but signal linearity may be degraded
Solution Approach 1:
The patent incorporates feedback mechanisms in the parallel delta-sigma modulator architecture where the quantization error from each parallel modulator is fed back and processed. This feedback ensures that even though un-constrained noise shaping filters are used (which simplify design), the overall signal linearity is maintained through error correction and distribution across multiple parallel paths, preventing linearity degradation
Data Source
AI summary
A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.