Time-Encoded Signal Multiplication Circuit for Low-Power Accuracy
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Solution Overview
Problem
Existing signal processing methods for multiplying analogue signals face challenges such as device mismatches, thermal drift, and high power consumption, particularly in battery-powered devices, where digital multiplication is often required but involves significant power and heat generation.
Innovation Solution
A processing circuit comprising time-encoding modulators, time-decoding converters, and a subtractor that generates PWM signals based on the square of combined input signals, allowing for efficient multiplication with reduced power consumption by converting analogue signals into digital outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital multiplication is implemented using conventional digital processing, then multiplication accuracy is improved, but power consumption increases and heat generation occurs
Solution Approach 1:
The patent replaces conventional digital multiplication (mechanical/logic gate operations) with a time-encoding modulation system that uses PWM signal generation and frequency measurement. The analog inputs are converted to time-encoded PWM signals whose frequencies represent the squared values of inputs, and multiplication is achieved through frequency comparison rather than traditional digital arithmetic operations, reducing power consumption while maintaining accuracy
Solution Approach 2:
The patent transforms the multiplication operation by changing the parameter domain from direct voltage/amplitude representation to frequency representation. By encoding input values as frequencies (where frequency ∝ input²) and performing multiplication through frequency relationships, the system achieves accurate multiplication with lower power consumption compared to conventional digital arithmetic
2Measurement precision
If conventional digital processing is used for signal multiplication, then calculation precision is improved, but the number of circuit nodes increases leading to higher power consumption
Solution Approach 1:
The patent replaces complex digital arithmetic circuitry (multiple logic gates and circuit nodes) with a time-encoding modulation approach. The system uses PWM modulators to encode inputs as time/frequency signals and a simple frequency counter to perform multiplication, dramatically reducing the number of active circuit nodes while preserving calculation precision through the mathematical relationships in the time domain
3Use of energy by moving object
If analogue circuit techniques are used for multiplying analogue signals, then power consumption is reduced, but device mismatches and thermal drift occur reducing reliability
Solution Approach 1:
The patent replaces purely analog multiplication circuits (which suffer from mismatches and drift) with a hybrid time-encoding system. By converting analog inputs to PWM signals and using frequency-based processing, the system maintains low power consumption while achieving immunity to analog component mismatches and thermal drift through the digital frequency measurement process
Solution Approach 2:
The patent introduces time-encoding modulation as an intermediary process between analog input signals and digital processing. The PWM modulator acts as a mediator that converts analog voltages into time-encoded frequency signals, eliminating the need for direct analog multiplication and its associated reliability issues while preserving the low-power advantage
Data Source
AI summary
This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D1, D2) and provides an output signal (DOUT) based on this difference.