Clock Delay Compensation in Photorepeated Integrated Circuits
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Solution Overview
Problem
Large-scale integrated circuits with repetitive juxtaposed patterns face signal propagation delays, leading to time shifts in clock signals across identical zones, which is not compatible with high-frequency operations, especially in circuits exceeding several centimeters in size.
Innovation Solution
The integration of a compensation circuit within each partial circuit, featuring a conductive compensation line with multiple outputs, a multiplexer, and buffer amplifiers, which introduces a controlled propagation delay to synchronize clock signals across adjacent circuits, ensuring simultaneous signal arrival.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the circuit size is increased to several centimeters to accommodate large-scale integration, then the integration capacity is improved, but the signal propagation delay increases causing time shifts in clock signals
Solution Approach 1:
The large integrated circuit is divided into N adjacent identical partial circuits, each receiving and processing clock signals independently. By segmenting the circuit, the patent enables localized clock signal distribution while maintaining synchronization across the entire large-scale circuit, thus accommodating increased circuit size without proportionally increasing propagation delays.
Solution Approach 2:
The patent introduces compensation circuits with delay lines in each partial circuit before the clock signal is distributed to functional units. These preliminary delay adjustments compensate for the propagation time differences that will occur during signal transmission across the large circuit, ensuring that clock signals arrive simultaneously at corresponding points in all partial circuits despite the increased overall circuit size.
2Productivity
If the operating frequency is increased to achieve high-speed operation, then the processing speed is improved, but the tolerance for signal propagation delays decreases making synchronization difficult
Solution Approach 1:
Each partial circuit is equipped with its own compensation circuit containing delay lines and multiplexers, allowing localized adjustment of clock signal timing. This local quality approach enables precise synchronization control in each segment independently, maintaining the synchronization precision required for high-frequency operation across the entire large-scale circuit.
Solution Approach 2:
The patent varies the delay parameters of the compensation lines and multiplexer selection signals across different partial circuits to compensate for propagation differences. By changing these timing parameters locally in each partial circuit, the system achieves precise clock synchronization even at high operating frequencies where timing margins are minimal.
3Manufacturing precision
If compensation circuits are added to each partial circuit to synchronize clock signals, then the signal synchronization is improved, but the device complexity increases
Solution Approach 1:
The patent uses identical patterns for all N partial circuits, including identical compensation circuits with delay lines and multiplexers. This copying approach allows the same synchronization mechanism to be replicated across all partial circuits, achieving precise clock synchronization while using standardized, proven circuit designs that reduce overall system complexity through reuse.
Solution Approach 2:
The compensation circuits serve multiple functions: they provide delay compensation, signal distribution, and synchronization control all within a single integrated block in each partial circuit. The multiplexer additionally routes both clock signals and control signals. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining synchronization precision.
Data Source
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AI summary
The invention relates to large integrated circuits fabricated by photorepetition of several identical partial patterns. More specifically, the invention relates to compensating for signal propagation delays (particularly clock signals) from one partial circuit to the next, where the signals must arrive simultaneously at the different partial circuits for proper operation of the system. The compensation circuit provided in each partial circuit (C1, C2, C3) comprises a main transmission line (LP) for a master clock signal and a compensation line (LS) with multiple outputs (S1, S2, S3), as well as a multiplexer for selecting one of the outputs, which differs in the various partial circuits. The multiplexer provides a local clock signal (ClkL1, ClkL2, ClkL3) in each partial circuit, and these clock signals are synchronous despite the propagation delays.