Current-Starved Clock Delay Circuit for Low-Power Edge Control
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Solution Overview
Problem
Existing sensor readout circuitry for IoT applications faces challenges in minimizing power dissipation while maintaining low power consumption, as current clock generation methods are prone to unwanted power consumption due to high short currents and long edge times.
Innovation Solution
A clock delay circuit is designed using a current mirror to generate a delayed clock signal, incorporating a capacitor and Schmitt trigger, which are current-starved to limit power dissipation, and a current steering digital-to-analog converter to configure delay times, reducing power consumption by controlling current flow during charging and discharging cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock generation circuitry is used in sensor readout circuitry, then the circuit can generate clock signals to sequence sensor operations, but the circuit suffers from high power dissipation due to high short currents and long edge times
Solution Approach 1:
The circuit employs periodic switching of the Schmitt trigger and inverter stages to generate delayed clock signals. The capacitive feedback network creates periodic charging and discharging cycles that generate clean clock edges with controlled duty cycles, reducing power dissipation while maintaining reliable signal generation.
Solution Approach 2:
The circuit changes the operating parameters of the delay elements by controlling the charging and discharging currents of the feedback capacitor through the Schmitt trigger. By adjusting the current levels and capacitor values, the delay time and edge characteristics can be optimized to reduce power dissipation while maintaining signal integrity.
2Use of energy by moving object
If the circuit is designed to minimize power dissipation, then battery life is extended, but the circuit complexity increases due to the need for current mirrors, Schmitt triggers, and configurable delay elements
Solution Approach 1:
The Schmitt trigger stage serves multiple functions: it provides hysteresis for clean signal transitions, acts as a current-controlled delay element, and generates the charging current for the feedback capacitor. This multi-functionality reduces the need for separate components, thereby reducing overall circuit complexity while maintaining low power operation.
Solution Approach 2:
The circuit implements nested current mirrors where the current mirror structures are embedded within the Schmitt trigger and inverter stages. This nesting allows shared transistors and current paths to perform multiple functions, reducing the total component count and simplifying the circuit layout while maintaining low power dissipation.
3Loss of time
If delay elements are used to generate delayed clock signals, then the circuit can control time durations for sensor operations, but the edge times become long causing high short currents
Solution Approach 1:
The circuit dynamically controls the charging and discharging currents of the feedback capacitor based on the input clock signal transitions. The Schmitt trigger provides dynamic current switching that adapts to the input signal edges, enabling precise delay control while minimizing the duration of high current states and reducing power loss.
Solution Approach 2:
The capacitive feedback network creates a regenerative effect where the output voltage is fed back to the input through the capacitor. This feedback mechanism sharpens the transition edges by providing positive feedback during switching, reducing the duration of high short currents while maintaining the desired delay time through the capacitor charging characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power dissipation by limiting short currents and optimizing edge times, enhancing the battery life of IoT sensors by configuring delay times based on capacitance, current scaling, and voltage thresholds, thereby improving the efficiency of clock generation in sensor readout circuitry.
Implementation Method 1
a capacitor configured to charge or discharge based on the input clock signal and an output clock signal, the capacitor having a capacitance (C)
Implementation Method 2
a current mirror configured to generate one or more starved currents based on the reference current and having a current scaling factor and configured to provide a scaled version of the reference current at the top node, scaled by a current scaling factor (NTOP)
Implementation Method 3
a Schmitt trigger configured to generate a Schmitt trigger output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a charging period of time (TCHARGE) correlated with TDEL, in response to a high signal input from the input clock signal, via the switching module, the high signal based on an upper threshold voltage (VST,High) of the Schmitt Trigger
Data Source
AI summary
A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (TCHARGE) correlated with TDEL. Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. TDEL is based on TCHARGE and TCHARGE is based on C, NTOP, VST,High, and a supply voltage.