Variable Clock Delay Circuit for Power-Noise Phase Compensation
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Solution Overview
Problem
Semiconductor apparatuses face synchronization issues due to phase differences between external and internal clock signals, which are not adequately compensated by existing delay locked loops (DLLs) or phase locked loops (PLLs), especially when power noise is introduced.
Innovation Solution
A clock signal delay circuit comprising a variable delay unit, a phase detection block, a control clock output block, and a delay control unit that dynamically adjusts the delay amount of the clock signal based on detected phase differences, using a toggling control clock signal to quickly compensate for phase mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay locked loop (DLL) is used to compensate for phase difference between external and internal clock signals, then synchronization is improved, but phase difference may still occur due to power noise and the compensation speed is insufficient
Solution Approach 1:
The patent implements dynamic phase compensation by making the delay amount adjustable based on detected phase difference. The variable delay unit changes its delay characteristic according to the phase difference between internal and external clock signals, enabling fast adaptation to phase changes caused by power noise while maintaining reliable synchronization.
Solution Approach 2:
The patent employs a feedback mechanism where the phase difference detection unit continuously monitors the phase difference between clock signals and feeds this information to the variable delay unit. This closed-loop feedback enables real-time compensation of phase differences, improving both synchronization reliability and compensation speed compared to fixed delay approaches.
2Device complexity
If the delay amount is fixed in the clock delay circuit, then the circuit structure is simple, but it cannot quickly compensate for phase differences caused by power noise
Solution Approach 1:
The patent transforms the fixed delay circuit into a dynamic one by introducing a variable delay unit whose delay amount can be adjusted. This dynamic characteristic allows the circuit to adapt to phase differences caused by power noise, significantly improving synchronization reliability while adding only moderate complexity through the inclusion of control logic.
Solution Approach 2:
The patent changes the delay parameter from a fixed value to a variable value that can be adjusted based on phase difference detection. By making the delay amount a controllable parameter rather than a fixed physical characteristic, the circuit gains the ability to compensate for phase variations while maintaining a relatively simple overall structure.
3Reliability
If a variable delay unit with adjustable delay amount is introduced to compensate for phase differences, then phase compensation capability is improved, but the circuit complexity increases
Solution Approach 1:
The patent divides the clock delay circuit into distinct functional modules: a variable delay unit for phase compensation, a phase difference detection unit for monitoring, and a control logic unit for coordination. This segmentation allows each module to perform its function efficiently while making the overall circuit complexity manageable through modular design.
Solution Approach 2:
The patent designs the variable delay unit to serve multiple functions: it compensates for phase differences caused by power noise, maintains synchronization between internal and external clock signals, and adapts to varying operating conditions. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
A clock signal delay circuit includes a variable delay unit, a delay unit, a phase detection block, a control clock output block, and a delay control unit. The variable delay unit controls a delay amount of a reference clock signal based on a delay control signal and provides a delayed clock signal based thereon. The delay unit delays the delayed clock signal and provides a feedback clock signal based thereon. The phase detection block detects a phase difference between the feedback clock signal and the reference clock signal and provides a detected phase difference based thereon. The control clock output block provides a control clock signal based on the detected phase difference. The delay control unit generates the delay control signal based on the detected phase difference and in response to the control clock signal.