Configurable Clock Distribution Across Multiple Frequency Domains
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Solution Overview
Problem
Existing clock distribution systems in digital circuits face challenges in efficiently distributing clock signals with varying frequencies, as high frequency signals increase power consumption and potential jitter, while low frequency signals may introduce jitter when locally increased, making it difficult to design a system that satisfies all applications.
Innovation Solution
A configurable clock generation circuit that outputs signals with multiple frequencies, allowing for field-programmable selection of frequencies and polarities to generate and distribute clock signals, enabling flexible clock distribution within a field-programmable device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency clock signals are distributed to meet the highest frequency requirements, then the clock frequency requirement is satisfied, but power consumption increases and jitter potential increases
Solution Approach 1:
The patent divides the clock distribution system into multiple independent clock trees, each serving specific frequency requirements. Instead of distributing one high-frequency clock throughout the entire device, separate clock trees are created for different frequency domains, allowing high-frequency clocks to be localized only where needed, thus reducing overall power consumption while meeting performance requirements.
Solution Approach 2:
The patent implements location-specific clock frequency assignment where different regions of the programmable logic device receive clock signals optimized for their specific requirements. High-frequency clocks are distributed only to regions requiring high performance, while other regions receive lower-frequency clocks, reducing unnecessary power consumption in areas that don't require high speed operation.
2Speed
If high frequency clock signals are distributed, then the clock frequency requirement is satisfied, but jitter and system noise increase
Solution Approach 1:
By segmenting the clock distribution into separate trees for different frequencies, the patent isolates high-frequency jitter and noise to specific localized regions. Low-frequency clock trees do not suffer from high-frequency jitter, and high-frequency regions are contained, preventing system-wide noise propagation.
Solution Approach 2:
The patent introduces clock management resources and buffer elements as intermediaries between clock sources and distribution networks. These intermediaries condition and clean clock signals, filtering out jitter and noise before distribution, thus protecting downstream logic from harmful high-frequency variations.
3Use of energy by moving object
If lower frequency clock signals are distributed and locally increased, then power consumption is reduced, but duty cycle variation introduces jitter
Solution Approach 1:
The patent creates dedicated high-frequency clock trees that are generated independently from low-frequency clocks. This segmentation eliminates the need to locally multiply low-frequency clocks in regions requiring high frequency, thus avoiding the jitter problem caused by duty cycle variations in frequency multiplication while still providing low power consumption in low-frequency regions.
4Adaptability or versatility
If a single clock distribution system is designed to satisfy all frequency requirements, then all locations can receive clock signals, but the system cannot optimize for different application requirements
Solution Approach 1:
The patent segments the clock distribution into multiple independent trees, each optimized for specific frequency ranges and application types. This allows the system to adapt to different application requirements by selectively activating appropriate clock trees, providing frequency flexibility while optimizing power consumption for each specific use case.
Solution Approach 2:
The patent implements dynamic clock distribution where the system can selectively enable or disable different clock trees based on the programmed logic requirements. This dynamic adaptation allows the clock distribution system to match the actual operational needs of the device, providing frequency versatility while minimizing power consumption by activating only the necessary clock frequencies.
Data Source
AI summary
A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.