Program Control Using Stored Programs TRIZ Cases
- Programmable Logic Memory Controller for External Memory Transfer
A dedicated memory controller built into programmable logic improves external memory data transfer and control signal handling.
- Memory Interface Cycle Calculation for Aligned Data Transfers
Logarithmic cycle calculation and address alignment handling cut memory access cycles for FPGA data transfers across memory boundaries.
- Configurable Clock Distribution Across Multiple Frequency Domains
Multiple clock trees and selectable local frequencies balance power use and jitter in programmable digital circuits.
- Memory Interface Transfer Control for Partial and Misaligned Data
A memory controller adjusts access cycles and time slots to move partial or misaligned data efficiently without wasting bandwidth.
- Configurable Word-Width Conversion Using Data Line Grouping
Configurable line grouping converts data between mismatched PLD and memory word widths, improving interface compatibility and transfer efficiency.
- Programmable Logic Memory Controller with Preconfigured Interfaces
A dedicated memory controller built into programmable logic before field programming improves external memory transfer efficiency and cuts interfacing complexity.
- Multi-Port Memory Arbitration with Configurable Time-Slot Priorities
Field-programmed time-slot priorities let multi-port memory arbitration accept the highest-priority pending command and improve transfer efficiency.
- Memory Controller Port Arbitration With Dynamic Priority Control
Dynamic enabling of memory controller command ports and a configurable priority list improve ordered data transfers while limiting arbitration complexity.
- Memory Interface Signal Calibration for Dynamic Clock-Data Alignment
Dynamic delay calibration aligns memory interface clock and data edges despite voltage and temperature shifts, avoiding read interruptions.
- Memory Controller Clock Delay Calibration During Refresh Cycles
Refresh-time tap adjustment keeps memory controller clock alignment stable under voltage and temperature shifts without stopping operation.
- Configurable Address Translation for PLD Memory Mapping
Programmable interconnect remaps byte addresses to bank, row, and column formats so PLDs can match different external memory devices.
- Multi-Storage Logic Configuration for Fast Function Switching
Multiple storage blocks let one function run while another is configured, cutting switching delay and improving logic response speed.
- Dispersed Media Storage Slicing for Secure Device Access
Encoded media slices are split across devices and locations, then completed on access to improve storage reliability without full-copy security risks.
- Preamble Detection Circuit for Asynchronous Signal Timing
A stored delay and preamble detection circuit aligns asynchronous control signals to improve PLD data capture from external memory.
- Memory Controller Suspend Handshake for DRAM Self-Refresh
Before suspend shuts down IC subsystems, the memory controller moves external memory into self-refresh to preserve data and acknowledge safe entry.
- Block-Based File Compression Using Per-Block Algorithms
Files are split into blocks so each part can use the best compression algorithm, handle large data sizes, and preserve file paths on restoration.
- Flat Audio Volume Control Across Complex Setting Hierarchies
A flat volume model maps one application-level control onto layered audio settings, making volume changes predictable without affecting other apps.
- Frame Buffer Bit-Splitting for Lower Streaming Data Bandwidth
Separating streaming data into MSB and LSB buffer regions enables selective access, cutting memory bandwidth waste without hurting retrieval performance.