Memory Interface Transfer Control for Partial and Misaligned Data
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory controllers in programmable logic devices (PLDs) are not optimal for transferring data that is not an integer multiple of the memory block size or that does not align with memory address boundaries, leading to inefficiencies in data transfer operations.
Innovation Solution
A memory controller system that includes a configurable structure to handle data transfers by determining the number of memory access cycles and time slots based on the data size and memory block size, allowing for partial block transfers and masking of unnecessary memory locations during read or write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed-width data port is used in the memory controller, then the device structure is simple, but it cannot efficiently handle data transfers that are not integer multiples of the block size or do not align with memory address boundaries
Solution Approach 1:
The data transfer process is segmented into multiple memory access cycles, where each cycle transfers a portion of the total data. The controller divides the data transfer task into discrete time slots (T) and bit groups (B), allowing flexible handling of arbitrary data sizes by adjusting the number of cycles (M) rather than changing the fundamental port structure.
Solution Approach 2:
The memory controller dynamically determines the number of memory access cycles (M) based on the data size to be transferred and the memory block size. This dynamic adjustment allows the system to adapt to different data transfer requirements while maintaining a fixed-width data port structure, resolving the contradiction between adaptability and structural simplicity.
2Productivity
If the memory controller transfers data in fixed block sizes, then the transfer operation is simple, but it cannot handle partial block transfers efficiently
Solution Approach 1:
The memory controller implements partial block transfers by allowing the data transfer quantity to be less than the full memory block size. The controller calculates the appropriate number of time slots to use within each memory access cycle, enabling efficient partial transfers without requiring complex additional hardware by simply controlling the transfer duration and scope.
Solution Approach 2:
The system changes the parameter of data transfer quantity from fixed block size to variable size based on actual needs. By dynamically adjusting the number of memory access cycles (M) and the subset of time slots used within each cycle, the controller achieves efficient partial block transfers while maintaining relatively simple operational mechanisms.
3Loss of energy
If the memory controller accesses entire memory blocks, then the memory access operation is simple, but it wastes bandwidth when transferring smaller amounts of data
Solution Approach 1:
The memory controller extracts and transfers only the necessary portion of data from each memory block, rather than accessing entire blocks. By calculating the precise number of time slots and cycles needed based on the data size to be transferred, the controller extracts only the required data elements, improving bandwidth utilization without requiring overly complex access control logic.
4Adaptability or versatility
If the memory controller uses alignment-based access, then the access operation is simple, but it cannot handle misaligned data transfers
Solution Approach 1:
The memory controller dynamically calculates the number of memory access cycles and time slots needed based on the specific data size and starting address. This dynamic approach allows the controller to handle misaligned transfers by adjusting the transfer parameters in real-time, achieving address boundary flexibility without requiring excessively complex address calculation logic beyond basic arithmetic operations.
Data Source
AI summary
An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M·T time slots; automatically determining a subset of the M·T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.