Configurable Address Translation for PLD Memory Mapping
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in translating memory addresses from internal byte address formats to the specific physical address formats required by external memory devices, as different devices have varying requirements for how byte address bits are split into bank, row, and column portions, leading to inefficiencies in address mapping.
Innovation Solution
A configurable interconnect structure within the PLD is programmed to electrically couple address terminals in a first subset to corresponding terminals in a second subset, allowing for selection of different mapping functions to match the address format of the connected external memory device, enabling flexible address translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed address mapping method is used, then the address translation is simple and fast, but the device cannot adapt to different external memory device formats
Solution Approach 1:
The patent implements a configurable interconnect structure that can dynamically reconfigure the mapping between byte address bits and physical address bits. The interconnect structure includes programmable switches and routing elements that can be programmed at runtime to support different address mapping schemes, allowing the same device to adapt to various external memory formats without hardware changes.
Solution Approach 2:
The invention changes the mapping parameters between address terminals by providing multiple configurable mapping functions. Each mapping function defines a different relationship between byte address bits and physical address bits (bank, row, column). The device can select and switch between these mapping functions based on which external memory device is connected, thereby adapting to different memory formats through parameter reconfiguration.
2Adaptability or versatility
If multiple address mapping functions are supported, then the device can interface with various memory devices, but the interconnect structure becomes more complex
Solution Approach 1:
The configurable interconnect structure serves multiple functions: it can implement different address mapping schemes, route signals between various internal blocks, and adapt to different external memory interfaces. By making the interconnect structure universal and reconfigurable, the patent supports multiple memory formats without requiring separate dedicated circuits for each format, thus managing complexity while maintaining versatility.
Solution Approach 2:
The interconnect structure is divided into multiple independent configurable segments or stages, where each stage can be independently programmed to perform specific mapping or routing functions. This segmentation allows complex address translation to be broken down into simpler, manageable stages, each handling a portion of the mapping task, thereby reducing overall structural complexity while supporting multiple formats.
3Ease of operation
If address bits are rigidly assigned to specific memory portions, then the address translation is straightforward, but the device cannot accommodate different memory configurations
Solution Approach 1:
The patent makes the address bit assignment dynamic rather than static. The interconnect structure can be reconfigured to assign different byte address bits to different physical address bits (bank, row, column) based on the memory configuration. This dynamic reassignment maintains simple address translation logic within each configuration while providing flexibility across multiple configurations.
Data Source
AI summary
A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.