Memory Controller Clock Delay Calibration During Refresh Cycles

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Solution Overview

Problem

Memory controllers in integrated circuits face misalignment issues due to variations in voltage and temperature, leading to potential data loss, as existing calibration methods require stopping operations and are time-consuming.

Innovation Solution

A dynamic signal calibration method within the IC, utilizing a delay circuit and measurement circuit, dynamically adjusts the delay applied to the clock signal by calculating a new tap setting during a refresh operation, ensuring continuous operation without interrupting the memory controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If re-calibration is performed by stopping memory controller operation, then signal alignment is restored, but system productivity decreases

Engineering Contradiction:

Improvesignal alignmentVSAvoidsystem operation continuity

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The calibration process is transformed from a static, interrupt-based operation to a dynamic, continuous process. The memory controller performs calibration during normal refresh operations, allowing the system to adapt to voltage and temperature variations without stopping operation. This dynamic approach maintains signal alignment while preserving system productivity.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The calibration function is integrated into the continuous refresh operation of the memory controller. Instead of interrupting the useful action of data transfer, the calibration is performed continuously during refresh cycles, ensuring signal alignment is maintained without breaking the operational flow of the system.

Inventive Principle:

Principle #20Continuity of useful action

2Reliability

If traditional calibration process is used, then signal alignment is achieved, but calibration time increases

Engineering Contradiction:

Improvesignal alignmentVSAvoidcalibration time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The calibration process is performed preliminarily during refresh operations before data transfer occurs. By integrating calibration into the refresh cycle, the system prepares the signal alignment in advance without requiring separate calibration time, thus eliminating the time loss associated with traditional calibration methods.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The calibration function is merged with the refresh operation of the memory controller. These two previously separate functions are combined into a single integrated process, allowing calibration to occur during refresh cycles without requiring additional time resources. This merging eliminates redundant operations and reduces overall calibration time.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8116162B1Dynamic signal calibration for a high speed memory controller

Publication Date: 2012.02.14 XILINX INC

AI summary

Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.