Clock Divider Hold Control for Glitch-Free Dynamic Frequency Scaling
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Solution Overview
Problem
Current dynamic frequency scaling processes in digital processing systems face complexity in controlling clock signal phase alignment, often resulting in glitches and system hangs when asynchronously changing divider settings without parking ongoing processes.
Innovation Solution
A clock distribution network with a state machine that asserts a hold signal to suspend divider operations and latch new divider values, ensuring synchronicity and preventing glitches by managing clock edges and phase reference clock thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous divider settings are changed to produce frequency changes, then frequency adaptability is improved, but system reliability deteriorates due to clock transients and system hangs
Solution Approach 1:
The state machine asserts a hold signal to pause the divider operation before latching a new divider setting. This preliminary action prevents clock transients by ensuring the divider is stationary during the configuration change, thereby maintaining system reliability while allowing frequency adaptability.
Solution Approach 2:
The state machine monitors the divider status and uses feedback signals to coordinate the hold assertion and deassertion timing. This feedback mechanism ensures that new divider settings are latched only when the divider is paused, preventing glitches and maintaining reliable operation while enabling dynamic frequency changes.
2Reliability
If synchronous DFS is implemented to preserve phase alignment, then system reliability is improved, but device complexity increases due to control complexity
Solution Approach 1:
The patent extracts the complex synchronous control logic from the frequency division process by using a hold signal mechanism. Instead of implementing complex synchronous DFS control, the system simply pauses the divider, latches the new setting, and resumes operation. This extraction reduces device complexity while maintaining reliability through the simplified state machine control.
3Productivity
If asynchronous divider changes are made without process parking, then productivity is improved, but manufacturing precision deteriorates due to clock glitches
Solution Approach 1:
The state machine applies preliminary anti-action by asserting the hold signal to prevent the divider from generating clock glitches during configuration changes. This counter-measure allows asynchronous divider changes to proceed without parking processes, improving productivity while maintaining clock signal precision by preventing harmful transients.
4Use of energy by moving object
If dynamic frequency scaling is implemented, then energy efficiency is improved, but device complexity increases due to control mechanisms
Solution Approach 1:
The state machine implements preliminary action by pausing the divider before configuration changes. This simple hold mechanism enables dynamic frequency scaling for energy efficiency without requiring complex control mechanisms, as the system only needs to assert and deassert a hold signal rather than implement sophisticated frequency management logic.
Data Source
AI summary
Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.