Clock Divider Circuit With Phase Extension for Odd Divisors
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Solution Overview
Problem
Existing clock dividers struggle to produce an output signal with a fifty percent duty cycle when dividing the input clock frequency by odd integers, limiting flexibility and component reuse in electronic circuits.
Innovation Solution
A clock divider circuit that modifies differential clock signals to extend one phase in every Ith cycle, allowing division by both odd and even numbers while maintaining a fifty percent duty cycle, using signal modifier circuitry and counting circuitry to switch the output signal value with control signals from a state machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock divider is designed to divide by even integers only, then it can easily produce a fifty percent duty cycle output, but it lacks flexibility to divide by odd integers
Solution Approach 1:
The circuit dynamically adjusts its operation mode based on whether the desired divisor is odd or even. For even divisors, it operates in a standard mode; for odd divisors, it activates a phase extension mechanism that dynamically modifies the clock signal phases to achieve the correct division ratio while maintaining fifty percent duty cycle
Solution Approach 2:
The clock divider is designed to perform multiple functions: it can divide by both even and odd integers while maintaining a fifty percent duty cycle. This is achieved by incorporating a universal architecture that includes phase extension circuitry and control logic that adapts the division process based on the desired divisor type
2Adaptability or versatility
If a clock divider is designed to divide by odd integers, then divisor flexibility is improved, but maintaining a fifty percent duty cycle becomes difficult
Solution Approach 1:
The circuit introduces asymmetric phase extension where one phase of the differential clock signal is extended in duration while the other phase is correspondingly reduced. This asymmetric modification allows odd integer division while maintaining overall symmetry in the output duty cycle, ensuring the high and low periods are equal
Solution Approach 2:
The circuit changes the temporal parameters of the clock phases by extending one phase duration and reducing the other. This parameter modification enables the circuit to achieve odd integer division ratios while maintaining the fifty percent duty cycle through compensatory phase adjustments
3Adaptability or versatility
If phase extension is applied to enable odd integer division, then divisor flexibility is improved, but signal distortion may occur
Solution Approach 1:
The circuit uses an intermediary differential signal structure where phase extension is applied to one phase while the other phase serves as a reference. This intermediary approach allows smooth transition and maintains signal integrity by using the differential pair to buffer and synchronize the phase changes
Data Source
AI summary
In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every Ith cycle, I being an integer. The clock divider also contains counting circuitry connected to change the value of an output signal each time I cycles of the variable clock signal are counted.