Counting Chain Pulse Counters TRIZ Cases

Temperature-shaped bias current lets a frequency divider track its minimum power point across process and temperature changes while avoiding LO buffer losses.

A PMOS-only 2-phase shift register cuts static current and transistor count, improving yield and lowering power in large OLED panels.

State-parked divider cells are preset before bypass or activation, enabling wide-range fractional-N division without clock glitches or frequency errors.

Pulse masking is timed across circuit blocks to divide clocks while stabilizing current consumption and reducing power-supply and EMI noise.

Two variable divider paths and a multiplexer extend integer clock division range while preserving high resolution at high input frequencies.

Cross-coupled logic blocks generate 25% or 75% output clocks directly, reducing I/Q imbalance and avoiding external clock gating.

Selectable n/m pulse output uses software counting and comparison to set integral pulse spacing without complex fixed hardware.

Counter-based phase monitoring corrects SD host sampling clocks during transfer and flags errors when temperature drift exceeds valid limits.

A shared clock input path keeps function and test clocks at the same insertion delay, enabling divided outputs with minimal skew.

Synchronized state transitions and a gray counter let one clock divider change division ratios without glitches, extra filters, or larger chip area.

A configurable I/O expander adds timer-synced outputs, capture, PWM, and PPM through one chip, avoiding microcontroller redesign.

Periodic receive modulation and pseudo-random transmit modulation spread clock energy to reduce EMI, spurs, and receiver desensitization.

Local pulse suppression and phase shifting at clock-tree leaves create slower B/C clocks while preserving timing synchronization between distant components.

Alternating gate-line outputs from panel-integrated shift register stages reduce LCD data lines and driver IC chips while preserving display driving.

Two counters and a toggle latch generate programmable clock duty cycles while helping reduce jitter and phase noise in timing-critical circuits.

Precharge and predischarge circuits cut parasitic capacitance, enabling a DLL frequency multiplier with low jitter and adjustable ratios.

Sequential phase selection enables fractional clock division without pulse-swallowing jitter, harmonics, or high prescalar power.

Correction logic between master-slave flip-flops keeps a divide-by-three CML prescaler stable above 1 GHz with a 50% duty cycle.

Common-mode even harmonics are fed back and amplified to multiply frequency with lower input power and better RF efficiency.

PMOS current sources and grounded NMOS substrates remove body-bias effects, cutting input voltage swing and power in latch-based dividers.

A delay-ring timing scheme generates clock periods from a single reference using real-number scaling, expanding frequency range with lower circuit complexity.

A phase stepper generates fractional clock frequencies with better jitter-power tradeoffs and less need for costly external PLL components.

Pre-charged differential buffer stages divide high input clocks with lower latency and power than flip-flop or CML approaches.

Measures picosecond duty cycle changes in GHz clock signals by sweeping frequency until a divider fails, avoiding costly or destructive tests.

A gated digital ring oscillator replaces DLL and PLL schemes to align data output with the input clock using less power and faster lock.

Temporary divisor changes shift clock phase forward or backward without divider reset, enabling flexible multi-clock timing control.

By extending one clock phase every Ith cycle, this divider supports odd and even division while preserving a 50% duty cycle.

Half-clock swallowing enables divide-by-N and N+0.5 switching, cutting quantization noise and supporting programmable synthesizers.

A microprocessor-based rate multiplier replaces fixed hardware logic, letting engineers adjust pulse intervals and n/m ratios without circuit redesign.

A counter-based clock delay shifts the sampling point to the stable data window, reducing jitter and skew in digital I/O timing.