Symmetrical Divide-by-Three Prescaler for High-Speed CML Clocks
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Solution Overview
Problem
Existing divide-by-three prescalers are not compatible with current-mode logic (CML) systems, particularly for frequencies above 1 GHz, as most designs fail to maintain a 50% duty cycle and stability in high-frequency applications.
Innovation Solution
A ring counter with a series of master-slave flip-flops and correction logic, including NAND and AND gates, is used to stabilize the prescaler, ensuring a 50% duty cycle and symmetrical rise and fall times by interposing logic gates between sequences of flip-flops to produce a clock signal divided by three, with an XOR gate for final output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional divide-by-three prescaler designs are used, then frequency division is achieved, but compatibility with CML systems and stability at frequencies above 1 GHz is not maintained
Solution Approach 1:
The patent changes the operational parameters of the prescaler by using master-slave flip-flop configurations and correction logic that are specifically optimized for CML operation at high frequencies. The correction logic modifies the timing and state transitions to maintain stability above 1 GHz while remaining compatible with CML system requirements.
Solution Approach 2:
The correction logic acts as an intermediary component between the master-slave flip-flops and the output stage. This correction logic gates the outputs to ensure proper state transitions and maintains the 50% duty cycle, thereby enabling compatibility with CML systems while preserving stability at high frequencies.
2Manufacturing precision
If conventional prescaler designs are used, then frequency division is achieved, but a 50% duty cycle with symmetrical rise and fall times is not maintained
Solution Approach 1:
The correction logic serves as an intermediary that gates the outputs of the master-slave flip-flops to enforce the 50% duty cycle. By inserting this correction stage, the patent achieves precise duty cycle control without requiring complete redesign of the entire prescaler structure, thus balancing precision with complexity.
Solution Approach 2:
The patent uses asymmetrical gating logic in the correction stage to compensate for any asymmetries in the master-slave flip-flop outputs. The correction logic applies different gating conditions to ensure that rise and fall times become symmetrical, achieving 50% duty cycle precision through controlled asymmetry in the correction stage.
Data Source
AI summary
Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these applications have experienced both decreases in size and increases in speed. As a result, current-mode logic or CML has come into use in some high speed applications, calling for alternative designs for components such as prescalers. Here, a divide-by-three prescaler is described that uses internal states from mater-slave flip-flop pairs and that is well-suited for microelectronics that employ CML.