Digital I/O Expander Chip with Reconfigurable Multi-Function Timer Cells
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Solution Overview
Problem
Microcontroller designs often require additional I/O functionality, which can involve complex and costly reengineering or the use of larger microcontrollers, CPLDs, or FPGAs, making it difficult to add advanced I/O functions efficiently.
Innovation Solution
A digital I/O expander chip with multiple user-configurable timer cells that can perform various functions such as parallel I/O, timer-synchronized outputs, input capture, pulse width/frequency measurement, and pulse position modulation, using a single integrated circuit with a simple serial or parallel interface, allowing for versatile I/O expansion without the need for extensive redesign.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional I/O functionality is added to existing microcontroller designs, then I/O capability is improved, but device complexity and reengineering cost increase
Solution Approach 1:
The patent introduces an I/O expander chip as an intermediary device that connects to the existing microcontroller via a simple serial interface. This mediator provides additional I/O functionality without requiring changes to the microcontroller's internal architecture or complex reengineering of the existing design. The expander chip handles the advanced I/O functions externally, maintaining system simplicity while enhancing capability.
Solution Approach 2:
The I/O expander chip implements multiple timer cells that can be configured to perform various functions including parallel I/O, timer-synchronized outputs, input capture, and pulse width modulation. This multi-functional design allows a single device to provide diverse I/O capabilities, reducing the need for multiple separate components or complex circuitry.
2Adaptability or versatility
If larger microcontrollers or CPLD/FPGA are used to provide additional I/O, then I/O capability is improved, but cost and development time increase
Solution Approach 1:
The patent segments the I/O functionality by separating it from the microcontroller and implementing it in a dedicated I/O expander chip. This segmentation allows the microcontroller to remain unchanged while adding advanced I/O capabilities in a separate, independently developable component. The serial interface provides a clean separation between the microcontroller and expander, enabling independent optimization of each part.
Solution Approach 2:
The I/O expander chip provides a copy of the necessary I/O functionality in a separate, pre-designed device. Rather than redesigning the entire microcontroller or using expensive CPLD/FPGA solutions, the patent uses a standardized expander chip that can be easily integrated into existing designs, significantly reducing development time and cost.
3Ease of manufacture
If simple I/O expansion is implemented, then ease of implementation is improved, but functionality remains limited
Solution Approach 1:
The I/O expander chip implements multiple timer cells that can be configured to perform various functions including parallel I/O, timer-synchronized outputs, input capture, and pulse width modulation. This multi-functional design allows a single device to provide diverse I/O capabilities, reducing the need for multiple separate components or complex circuitry.
Solution Approach 2:
The timer cells in the I/O expander can be dynamically reconfigured through software to perform different functions. This dynamic adaptability allows the same hardware to serve multiple purposes, from simple I/O expansion to complex timing and modulation tasks, maintaining implementation simplicity while enhancing functionality.
Data Source
AI summary
A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.