State-Parked Multi-Modulus Divider for Glitch-Free Ratio Switching
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Solution Overview
Problem
Conventional fractional-N frequency synthesizers with multi-modulus dividers suffer from frequency errors and clock glitches when changing division ratios, requiring complex high-speed circuitry to recover from these glitches.
Innovation Solution
A multi-modulus divider with state-parked dual modulus divider cells connected in cascade and ripple configuration, where the last (n-k) cells can be bypassed and set to a predetermined logical state using programmability bits, allowing seamless transition between different numbers of divider cells without clock errors, utilizing a multiplexer to select the appropriate output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional multi-modulus dividers are used to cover a wide division range, then the division range is extended, but frequency errors and clock glitches occur when the number of divider cells changes
Solution Approach 1:
The patent applies preliminary action by pre-setting the state-parked divider cells to a predetermined logical state (all zeros) before they are activated. This preliminary state preparation ensures that when divider cells are added or removed from the cascade, there are no transient glitches or frequency errors, as the newly activated cells are already in a known stable state rather than transitioning from an undefined state.
Solution Approach 2:
The patent introduces an intermediary mechanism - the state-parked divider cells with forced predetermined logical states - that mediates between the changing number of active divider cells and the overall division operation. These intermediary cells act as buffers that maintain signal integrity during transitions, preventing glitches from propagating through the cascade when the configuration changes.
2Adaptability or versatility
If conventional multi-modulus dividers are used to cover a wide division range, then the division range is extended, but complex high-speed circuitry is required to recover from glitches
Solution Approach 1:
By pre-setting the state-parked divider cells to a predetermined logical state before activation, the patent eliminates the need for complex high-speed glitch recovery circuitry. The preliminary state preparation prevents glitches at their source, simplifying the overall circuit design compared to conventional approaches that require additional high-speed recovery mechanisms.
Solution Approach 2:
The patent extracts and removes the problematic element - the glitch generation mechanism - by ensuring state-parked cells are pre-initialized to a stable state. This extraction approach eliminates the need for complex recovery circuitry that would otherwise be required to correct glitches, thereby reducing device complexity while maintaining wide division range capability.
3Measurement precision
If the number of divider cells changes to adjust division ratio, then frequency resolution is improved, but clock errors and glitches occur during transition
Solution Approach 1:
The patent applies preliminary action by pre-initializing state-parked divider cells to a predetermined logical state before they are activated during division ratio changes. This ensures that when the number of divider cells changes to achieve fine frequency resolution, the transition is smooth and free from clock errors, as the newly activated cells are already in a stable known state.
4Reliability
If conventional dividers are used, then high-speed control signals are needed to correct glitches, but this increases the speed requirements and complexity of control circuitry
Solution Approach 1:
By pre-setting state-parked divider cells to a predetermined logical state before activation, the patent achieves glitch-free operation without requiring high-speed control signals. The preliminary state preparation eliminates glitches at their source, allowing control signals to operate at lower speeds and reducing the speed requirements for control circuitry compared to conventional approaches that require high-speed glitch correction.
Data Source
AI summary
A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.