Glitch-Free Clock Scaling Circuit Using Phase-Shifted Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock switching in low power and high performance applications often results in glitches due to simultaneous transitions of clock lines, which is inappropriate for built-in self test circuits and requires additional dead time or clamping, unsuitable for certain applications.
Innovation Solution
Generating two phase clocks from a master clock, where one is in phase and the other 180 degrees out of phase, allowing for glitch-free switching by ensuring non-overlapping transitions and eliminating the need for dead time or clamping, with programmable frequency selection and switching within half the period of the new clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock switching is performed by dividing the system clock and switching to low frequency clock, then power consumption is reduced and performance is optimized, but glitches occur on clock lines causing circuit malfunctioning
Solution Approach 1:
The patent applies preliminary action by generating the divided clock signal in advance before the switching event occurs. The divided clock signal is prepared and held ready, and the switching is performed by simply selecting between the original and divided clock signals based on control signals, rather than performing the division operation at the moment of switching. This eliminates glitches by avoiding simultaneous transitions during clock frequency changes.
Solution Approach 2:
The patent uses control signals as an intermediary mechanism to manage the clock switching process. The control signals coordinate the selection between different clock frequencies without causing direct conflicts or simultaneous transitions. This intermediary control layer ensures that switching occurs cleanly by managing the transition timing and selection logic.
2Reliability
If multi-cycle dead time is introduced between clock switching, then glitches are prevented, but switching speed is reduced and productivity is lowered
Solution Approach 1:
The patent eliminates the need for multi-cycle dead time by preparing the divided clock signal in advance. The clock division operation is performed before switching is needed, and the results are held ready for immediate selection. This allows instantaneous switching between clock frequencies without requiring waiting periods or dead time, thereby maintaining high switching speed while preventing glitches.
Solution Approach 2:
The patent implements dynamic clock frequency switching by using control signals that can immediately select between different clock frequencies based on current system conditions. The switching mechanism is designed to be responsive and adaptive, allowing the system to transition between high and low frequency modes rapidly without fixed timing constraints or dead time requirements.
3Productivity
If clock switching is performed without dead time, then productivity is maintained, but glitches may occur causing circuit malfunctioning
Solution Approach 1:
The patent resolves this contradiction by performing the clock division operation in advance and holding the divided clock signal ready for immediate use. When switching is required, the system simply selects between the original and pre-divided clock signals without performing any division operation at the switching moment. This preliminary preparation enables instantaneous switching without glitches, maintaining both high productivity and reliability.
4Reliability
If two phase clocks are generated with 180 degrees phase difference, then non-overlapping transitions are achieved eliminating glitches, but device complexity increases
Solution Approach 1:
The patent reduces the need for complex phase manipulation by performing the clock division operation in advance and using the divided clock signal directly for switching control. This preliminary preparation simplifies the switching logic, as the system only needs to select between pre-prepared clock signals rather than dynamically managing phase relationships during switching events.
Data Source
AI summary
Techniques for scaling and switching clocks in a glitch-free manner are provided. For example, in one aspect of the present invention, a technique for switching a frequency associated with a master clock includes the following steps/operations. Two phase clocks are generated from a master clock, wherein the two phase clocks do not transition at substantially the same time. Then, one of the two phase clocks is used to create multiple frequencies by dividing the one phase clock, and the other phase clock is used to switch between the multiple frequencies of the one phase clock. Further, one of the two phase clocks may be in phase with the master clock and the other of the two phase clocks may be 180 degrees out of phase with the master clock such that they do not transition at the same time. Also, the two phase clocks may be non-overlapping.