Differential Divider Circuit for High-Frequency Low-Power Clocking
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Solution Overview
Problem
Conventional frequency divider circuits using flip-flops face limitations at high input clock frequencies due to DQ delay time, leading to increased power consumption and complexity when switching to Current Mode Logic, which is undesirable in low-power mobile radio applications.
Innovation Solution
A divider circuit employing at least two clock edge controlled differential buffer store elements with pre-chargeable internal storage nodes, allowing for pulsed signals to be tapped off and used in a fixed phase relationship, thereby minimizing latency and power consumption while maintaining high frequency division capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional flip-flops are used in CMOS technology, then power consumption is low, but the DQ delay time limits the maximum input frequency
Solution Approach 1:
The flip-flop is divided into two separate stages: a differential sense amplifier stage that captures the input signal on the rising edge, and an RS flip-flop stage that latches the signal on the falling edge. This segmentation allows each stage to operate optimally at different clock phases, effectively doubling the maximum input frequency while maintaining CMOS low-power characteristics
Solution Approach 2:
The differential sense amplifier stage performs preliminary signal amplification and level conversion before the main latching operation. By pre-processing the signal during the rising edge, the subsequent RS flip-flop stage can operate more efficiently during the falling edge, reducing overall delay time without increasing static power consumption
2Speed
If CML circuitry is used to increase speed, then the maximum input frequency increases, but power consumption and circuit complexity increase due to constant current flow and level conversion requirements
Solution Approach 1:
The invention uses dynamic nodes that are pre-charged during each clock cycle and then discharged through controlled switching. These temporary charge states are intentionally short-lived and regenerated each cycle, allowing high-speed operation without the need for CML's continuous current flow, thus maintaining low static power consumption while achieving high frequency operation
Solution Approach 2:
The circuit dynamically changes the operational mode of the buffer store elements based on the clock phase: during the rising edge, the sense amplifier stage is active with high gain for signal detection; during the falling edge, the RS flip-flop stage latches the signal. This parameter switching allows the circuit to achieve CML-like speed without CML's high power consumption
3Speed
If CML circuit parts are used for fast divider circuits, then speed increases, but additional circuit complexity and power loss occur due to level conversion for CMOS signals
Solution Approach 1:
The differential buffer store elements serve multiple functions within a single integrated structure: they act as differential amplifiers during the rising edge, as latching elements during the falling edge, and as level converters between differential and single-ended signals. This multi-functionality eliminates the need for separate CML-to-CMOS level conversion circuits, reducing overall circuit complexity while maintaining high speed operation
Data Source
AI summary
A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.