State-Machine Clock Divider for Glitch-Free Ratio Switching
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Solution Overview
Problem
Conventional clock dividers require increased chip size and power consumption due to the need for multiple division ratios and often experience glitches when changing division ratios, necessitating additional circuits like glitch filters.
Innovation Solution
A clock divider design utilizing a state machine with D flip-flops and a counter, including a control signal generating unit and state update unit, which allows for various division ratios without the need for additional glitch filters by synchronizing state transitions with a clock signal and using a gray counter to minimize errors at high speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock dividers with predetermined division ratios are used, then various division ratios can be generated, but chip size increases in proportion to the number of division ratios
Solution Approach 1:
A single clock divider circuit is designed to perform multiple division ratios (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16) by using a state machine with controllable transition paths. The division ratio is selected through control signals (S0-S2) that determine the state transition behavior, allowing one circuit to replace multiple dedicated dividers.
Solution Approach 2:
The clock divider uses a dynamic state machine where the division ratio can be changed during operation by modifying control signals. The state transitions are dynamically adjusted based on the selected division ratio, enabling flexible reconfiguration without hardware changes.
2Adaptability or versatility
If multiple clock dividers with predetermined division ratios are used, then various division ratios can be generated, but power consumption increases
Solution Approach 1:
One power-consuming circuit is designed to handle all division ratios through software/control signal configuration rather than having multiple parallel circuits each consuming power. This significantly reduces total power consumption while maintaining full functionality.
3Adaptability or versatility
If conventional clock dividers change division ratio, then output signal division ratio changes, but glitches occur requiring additional glitch filter circuits
Solution Approach 1:
The state machine is designed to pre-synchronize state transitions with clock edges before changing division ratios. Control signals are managed to ensure smooth transitions without generating glitches, eliminating the need for additional glitch filter circuits.
Solution Approach 2:
The clock divider incorporates feedback mechanisms where state transitions are monitored and controlled to maintain signal integrity during division ratio changes. The control logic ensures that transitions occur at appropriate clock edges, preventing glitch generation.
4Reliability
If additional glitch filter circuits are added to prevent glitches, then signal stability improves, but chip size increases
Solution Approach 1:
Instead of adding complex glitch filter circuits, the design converts the potential harm of glitches into benefit by using synchronized state transitions that naturally prevent glitch generation. The control mechanism turns a potential problem into a design feature.
5Reliability
If additional glitch filter circuits are added to prevent glitches, then signal stability improves, but power consumption increases
Solution Approach 1:
The design eliminates the need for additional power-consuming glitch filter circuits by incorporating glitch-prevention logic directly into the state machine control. This approach maintains signal stability without the extra power cost of separate filter circuits.
Data Source
AI summary
A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in synchronization with a clock signal. The second state storage unit performs transition of a second state value in synchronization with a first state signal corresponding to the first state value. The first control signal generating unit generates a first control signal for determining a first state transition path based on a first division ratio control signal. The state update unit generates the update signal based on the first control signal and the first state signal. The output unit selectively output the first state signal or a second state signal corresponding to the second state value.