Latch-Based Frequency Divider With Reduced Input Voltage Swing
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Solution Overview
Problem
Conventional frequency dividers, such as divide-by-two circuits, face limitations due to the body-bias effect in NMOS transistors, which require high voltage swings for proper operation, leading to increased power consumption and potential performance constraints in electronic circuits like GPS receivers and CDMA transceivers.
Innovation Solution
The design incorporates latch circuits with PMOS transistors as current sources and NMOS transistors with substrates coupled to ground, eliminating the body-bias effect and reducing the voltage swing requirements for input signals, while maintaining the same output voltage swing as conventional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional latch circuits with NMOS transistors are used in frequency dividers, then the circuit can operate, but high voltage swings are required due to the body-bias effect, leading to increased power consumption
Solution Approach 1:
The patent changes the substrate connection parameter of NMOS transistors from conventional connections to ground connection, which eliminates the body-bias effect. This parameter change allows the transistors to operate with smaller voltage swings while maintaining proper function, directly reducing power consumption in the frequency divider circuit
Solution Approach 2:
The patent uses PMOS transistors as current sources to replicate the function of conventional current generation circuits. By copying and adapting proven circuit topologies with the modified NMOS substrate connection, the design achieves reduced power consumption without sacrificing operational reliability
2Device complexity
If NMOS transistors with conventional substrate connections are used, then the circuit structure is simple, but the body-bias effect increases voltage swing requirements and may require additional buffers
Solution Approach 1:
The patent modifies the substrate connection parameter of NMOS transistors to ground connection, which eliminates the body-bias effect. This single parameter change reduces voltage swing requirements without adding circuit complexity, as no additional buffers or components are needed
Solution Approach 2:
The patent extracts and eliminates the body-bias effect by changing the substrate connection, removing the harmful factor that caused increased voltage swing requirements. This extraction approach maintains circuit simplicity while solving the operational constraint
3Reliability
If higher voltage swings are provided to overcome body-bias effect, then proper operation is achieved, but power consumption increases and performance is constrained
Solution Approach 1:
The patent changes the substrate connection parameter to eliminate the body-bias effect, allowing proper operation to be achieved with smaller voltage swings. This parameter modification directly reduces power consumption while maintaining reliable circuit operation
Solution Approach 2:
The patent converts the harmful body-bias effect into a benefit by changing the substrate connection to ground. This transformation eliminates the voltage swing requirement issue while maintaining proper transistor operation, effectively turning a design constraint into an advantage
Data Source
AI summary
A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source current, a second level for receiving a pair of input signals and for generating a pair of output signals, and a third level for receiving the source current and a pair of clock signals. The second level is coupled between the first level and the third level. The first level includes a first transistor having a source terminal and a substrate both coupled to a source voltage. The third level includes a plurality of transistors controlled by the pair of clock signals. Each transistor in the third level has a source terminal and a substrate both coupled to ground.