Digital I/O Clock Delay Control for Stable Data Sampling
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Solution Overview
Problem
Existing data communication systems face challenges in accurately sampling data signals due to system noise, clock jitter, and phase skew between clock signals and data signals, which are not effectively addressed by traditional delay-locked loop circuits.
Innovation Solution
A delay count generator and slave delay module are used to apply a desired phase shift to an input clock signal, generating a delayed clock signal by counting cycles of a high-frequency clock signal and controlling the counting operation based on the input clock signal, allowing for precise sampling of data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DLL circuits with phase comparisons are used for timing control, then clock phase shifting capability is achieved, but system stability deteriorates due to phase comparison instability
Solution Approach 1:
The patent extracts and removes the unstable phase comparison function from the timing control system. Instead of using DLL circuits that perform phase comparisons, the invention uses a simple counter-based delay control mechanism that counts clock cycles to achieve delay without requiring unstable phase comparison operations.
Solution Approach 2:
The patent replaces the mechanical/electrical phase comparison mechanism with a digital counting mechanism. The delay is achieved by counting clock cycles using a counter circuit, which is inherently more stable than phase comparison methods. This substitution eliminates the stability issues associated with phase comparisons while maintaining the ability to control clock delay.
2Manufacturing precision
If multiple delay blocks are used in DLL circuits, then precise timing control is achieved, but device complexity increases
Solution Approach 1:
The patent changes the control parameter from continuous phase adjustment (requiring multiple delay blocks) to discrete clock cycle counting. By controlling the number of clock cycles counted, the system achieves precise timing control with a single counter circuit instead of multiple delay blocks, thereby reducing complexity while maintaining precision.
Solution Approach 2:
The patent makes a single counter circuit perform the timing control function that previously required multiple specialized delay blocks. The counter can be programmed to count any number of clock cycles, providing universal timing control capability that replaces multiple fixed-function delay elements, thus reducing overall device complexity.
3Speed
If data sampling is performed close to clock edges, then sampling speed is improved, but sampling accuracy deteriorates due to noise and skew
Solution Approach 1:
The patent applies delay control to advance the sampling clock edge timing before data arrives at the sampler. By pre-calculating and applying the appropriate delay, the system positions the sampling edge optimally within the data valid window, ensuring accurate sampling without requiring the sampler to operate at the极限 of its speed capability.
Data Source
AI summary
When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.