Multi-Phase Fractional Divider for Jitter-Free Clock Division
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Solution Overview
Problem
Conventional phase locked loop dividers generate jitter and glitches when dividing input clock frequencies by fractional ratios, limiting their application in high-performance synthesizers due to undesirable harmonic components and power consumption.
Innovation Solution
A divider system that dynamically selects phases of an input signal to achieve jitter-free fractional division by using a counter circuit and multiplexer to trigger and select corresponding phases, allowing division by fractional ratios like N+0.75, N+0.5, and N+0.25 without power-intensive pulse-swallowing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pulse-swallowing technique is used to obtain fractional division ratios, then non-integer and odd-inter ratios can be obtained, but undesirable harmonic frequencies components and pulse jitter are generated
Solution Approach 1:
The fractional division process is segmented into multiple integer division stages. The divider circuit performs sequential integer divisions (e.g., divide by 2, then by 3) to achieve the overall fractional division ratio, avoiding the need for pulse-swallowing while eliminating harmful harmonics and jitter
Solution Approach 2:
The divider dynamically switches between different integer division ratios based on control signals. The division ratio is changed over time through controlled switching between different divide-by-N circuits, enabling fractional division without the harmful effects of pulse-swallowing techniques
2Adaptability or versatility
If pulse-swallowing technique is used to obtain fractional division ratios, then desired division ratios can be achieved, but pulse jitter is generated
Solution Approach 1:
The fractional division is segmented into multiple stable integer division stages, each with well-defined timing characteristics. By breaking down the fractional division into sequential integer divisions, pulse timing stability is maintained while achieving the desired fractional ratio
Solution Approach 2:
Multiple clock phases are generated as copies of the input clock, each divided by different integer ratios. These copied and divided phases are then selectively combined to achieve the fractional division ratio without introducing jitter, as each copy maintains the original timing integrity
3Ease of operation
If conventional divider circuits are used for fractional division, then frequency control is achieved, but power consumption increases
Solution Approach 1:
The divider uses dynamic switching between different integer division circuits based on control signals. By dynamically selecting which division circuit to use and for how long, the system achieves fractional division with lower average power consumption compared to conventional approaches that require continuous operation of complex fractional division logic
Solution Approach 2:
The divider operates in periodic cycles, alternating between different integer division ratios. Each cycle uses simple integer division circuits that consume minimal power, and the periodic switching between different ratios achieves the overall fractional division effect without requiring power-intensive continuous fractional division circuitry
Data Source
AI summary
A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.