Programmable Clock Divider Using a Common Path to Prevent Clock Skew
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Solution Overview
Problem
In integrated systems, clock dividers often introduce phase shifts or clock skew when providing clock signals to components operating at different frequencies, complicating synchronization and testing functionalities.
Innovation Solution
A programmable clock divider with a common clock signal input path for both function and test clocks, using multiplexers and logic units to ensure consistent insertion delay and flexible frequency ratio adjustment, allowing for synchronized clock division and testing without phase shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clock dividers are used to provide clock signals at different frequencies, then frequency division is achieved, but phase shift or clock skew is introduced in rising edges
Solution Approach 1:
The patent introduces a common clock path as an intermediary mechanism that receives both the function clock and test clock, ensuring they experience identical insertion delays. This mediator structure (common path 305) synchronizes the rising edges of both clocks before they enter their respective division paths, eliminating phase shifts without affecting the frequency division function.
2Adaptability or versatility
If separate clock paths are used for function and test clocks, then independent operation is achieved, but different insertion delays cause phase shifts
Solution Approach 1:
The patent merges the function clock and test clock into a common clock path 305 for initial processing. This combining approach ensures both clocks receive identical insertion delays in the shared path, while subsequent separate paths (310 for function, 320 for test) maintain independent operation. The merger resolves the contradiction by providing both unity in delay experience and diversity in operational independence.
3Device complexity
If clock division is implemented without a common path, then device complexity is reduced, but phase synchronization between function and test clocks deteriorates
Solution Approach 1:
The patent segments the clock path into three distinct sections: a common path 305 for synchronized input processing, a function path 310 for operational clock division, and a test path 320 for testing clock division. This segmentation allows the system to maintain simple, modular structures while ensuring phase synchronization occurs in the shared section, thereby achieving both low complexity and high reliability.
Data Source
AI summary
In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.