Cross-Coupled Frequency Divider for Non-50% Duty Cycle Clocks
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Solution Overview
Problem
Conventional frequency dividers cannot generate output clock signals with a duty cycle different from the input clock signal, leading to I/Q imbalance and weak driving capability in wireless receivers, as they require external signal processing to achieve desired duty cycles.
Innovation Solution
A frequency divider design incorporating logic circuit blocks with cross-coupled connections and transistors, allowing for the direct generation of output clock signals with a duty cycle different from the input clock signal, eliminating the need for external clock-gating circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional frequency divider is used to divide the frequency of an input clock signal, then the frequency is divided successfully, but the duty cycle of the output clock signal remains identical to the input clock signal's duty cycle
Solution Approach 1:
The frequency divider is divided into multiple logic circuit blocks (first logic circuit block, second logic circuit block, third logic circuit block, fourth logic circuit block), each performing specific functions. This segmentation allows different blocks to handle frequency division and duty cycle modification independently, resolving the contradiction between frequency division capability and duty cycle adaptability.
Solution Approach 2:
Intermediate clock signals are generated as mediators between the input clock signal and the final output clock signal. These intermediate signals with adjusted duty cycles are used to control the switching of transistors in subsequent logic blocks, enabling the final output to have a different duty cycle than the input while maintaining proper frequency division.
2Adaptability or versatility
If external signal processing circuits are added to modify the duty cycle of output clock signals from a conventional frequency divider, then the desired duty cycle can be achieved, but the device complexity increases
Solution Approach 1:
The duty cycle modification function is merged into the frequency divider itself by integrating logic circuit blocks with specific transistor configurations directly into the frequency division architecture. This eliminates the need for separate external signal processing circuits, reducing overall device complexity while maintaining duty cycle control capability.
Solution Approach 2:
The logic circuit blocks within the frequency divider are designed to perform multiple functions: frequency division and duty cycle adjustment. By making these blocks universal, the circuit can achieve different output duty cycles (e.g., 25%, 75%) without requiring additional dedicated circuits, thereby reducing complexity while enhancing adaptability.
3Adaptability or versatility
If clock-gating circuits are used to generate desired duty cycle clock signals from conventional frequency divider outputs, then duty cycle adjustment is possible, but I/Q imbalance sensitivity to phase error increases
Solution Approach 1:
The duty cycle adjustment is performed preliminarily within the frequency divider before the clock signals are used in subsequent I/Q processing stages. By pre-adjusting the duty cycle of the output clock signals to exactly 25% or 75% through the logic circuit blocks, the system eliminates the need for post-processing clock-gating operations that would introduce phase errors and I/Q imbalance sensitivity.
4Adaptability or versatility
If signal processing circuits are implemented externally to process clock signals for duty cycle modification, then the desired duty cycle can be achieved, but the driving capability of the output clock signal becomes weak
Solution Approach 1:
The logic circuit blocks within the frequency divider generate the output clock signals directly with the desired duty cycle and sufficient driving capability. The circuit serves itself by internally producing the correctly conditioned clock signals without requiring weak external signal processing circuits, thereby maintaining strong driving capability while achieving duty cycle control.
Data Source
AI summary
A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.