Clock Divider Phase Adjustment Without Reset
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Solution Overview
Problem
Existing clock-generating circuits struggle to dynamically control the phase difference between multiple clock signals without resetting dividers, limiting their ability to generate desired relative phase shifts.
Innovation Solution
A clock-processing circuit comprising a divider and a divisor control circuit that adjusts the divisor value to achieve selected phase shifts in the output clock signal without resetting the divider, using a load-once circuit to temporarily change the divisor value during each cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the phase of the second clock signal is dynamically controlled, then the adaptability of the clock-generating circuit is improved, but the device complexity increases due to the need for additional control circuits
Solution Approach 1:
The divisor control circuit serves multiple functions: it controls the division ratio of the divider to generate different frequency clock signals, and simultaneously controls the phase of the output clock signal by dynamically adjusting the divisor value. This multi-functionality allows the circuit to achieve both frequency division and phase control without requiring separate dedicated circuits, thereby improving adaptability while limiting the increase in complexity.
Solution Approach 2:
The invention changes the divisor parameter of the divider dynamically to achieve phase control. By adjusting the divisor value according to the desired phase shift, the circuit can generate clock signals with different phases and frequencies using the same hardware structure, thereby achieving adaptability without proportionally increasing device complexity.
2Adaptability or versatility
If the divider is reset to achieve desired phase delay, then the phase control capability is improved, but the productivity decreases due to the need for resetting operations
Solution Approach 1:
The invention transitions from a static phase control approach (requiring divider reset) to a dynamic approach where the divisor value is continuously adjustable. The divisor control circuit dynamically modifies the divisor parameter during operation to achieve the desired phase delay, eliminating the need for disruptive reset operations and thereby maintaining continuous clock signal generation and improving productivity.
Solution Approach 2:
The divisor control circuit calculates and prepares the appropriate divisor value in advance to achieve the desired phase shift, then applies this pre-calculated value to the divider. This preliminary preparation of the divisor parameter allows for smooth phase transitions without requiring divider reset, thereby maintaining operational efficiency and productivity.
3Device complexity
If prior-art circuits only delay the phase, then the device complexity is reduced, but the adaptability is worsened by inability to advance phase
Solution Approach 1:
By making the divisor parameter dynamically adjustable, the circuit can achieve both phase delay (by increasing the divisor value) and phase advance (by decreasing the divisor value) relative to the reference clock signal. This parameter-based control approach provides bidirectional phase adjustment capability within the same circuit structure, thereby improving adaptability without requiring fundamentally different circuit architectures.
Data Source
AI summary
In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.