Phase-Stepper Signal Generator for Fractional Clock Synthesis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional signal generator circuits in phase-locked loops face challenges in achieving optimal jitter performance and power consumption when generating clock signals of different frequencies, often requiring large loop filters or external components, which can be costly and power-intensive.
Innovation Solution
A signal generator circuit incorporating an oscillator and a phase stepper circuit that generates a second signal with a fractional multiple or division of the primary frequency, utilizing a phase stepper circuit to switch phases based on control signals, thereby improving jitter performance while balancing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional PLL is used to generate a 36.864 MHz clock from a 30 MHz reference clock with a divide value of 625, then the desired clock frequency is achieved, but the jitter performance is poor
Solution Approach 1:
The patent segments the frequency multiplication process into two stages: first multiplying by a factor (e.g., 2.5x to get 75 MHz), then using a second PLL stage to achieve the final frequency. This segmentation allows each stage to operate with more favorable parameters, improving overall jitter performance while maintaining frequency accuracy.
Solution Approach 2:
The patent introduces an intermediate frequency stage (e.g., 75 MHz or 184.32 MHz) as a mediator between the reference clock and the final output frequency. This intermediary frequency allows the phase detector to operate at higher rates, improving jitter performance, while the second PLL stage ensures the final frequency accuracy is maintained.
2Measurement precision
If the VCO output frequency is increased to 184.32 MHz to improve phase detector rate, then jitter performance is improved, but power consumption is increased
Solution Approach 1:
The patent divides the frequency multiplication into two stages, allowing the first VCO to operate at a moderate frequency (e.g., 75 MHz) rather than requiring a single high-frequency VCO. This segmentation reduces the power consumption of the VCO while still achieving high phase detector rates in the second stage, thus improving jitter performance without excessive power consumption.
Solution Approach 2:
The patent uses dynamic frequency multiplication where the multiplication factor is achieved through a combination of VCO frequency and programmable divider ratios. This allows flexible optimization of the VCO frequency to balance between power consumption and phase detector rate, rather than being locked into a single high-frequency operating point.
3Productivity
If the VCO output frequency is increased to 921.6 MHz to further increase phase detector rate, then the phase detector rate increases, but power consumption increases and may not be possible in slower technologies
Solution Approach 1:
The patent segments the frequency multiplication process so that the first stage achieves a moderate multiplication (e.g., 2.5x to 75 MHz), and the second stage completes the multiplication. This segmentation allows the use of lower VCO frequencies that are achievable in slower technologies, while still achieving high effective phase detector rates through the combined multiplication effect, thus reducing power consumption and improving manufacturability.
Solution Approach 2:
The patent uses a first PLL stage that performs partial frequency multiplication (e.g., 2.5x) before the second stage. This partial action in the first stage reduces the burden on the second stage, allowing the use of lower VCO frequencies and reducing overall power consumption while achieving the required phase detector rate through the cumulative effect of both stages.
4Manufacturing precision
If a conventional PLL is used with a large loop filter or external components, then the desired frequency generation is achieved, but the cost increases
Solution Approach 1:
The patent merges the frequency multiplication function into the PLL architecture itself by using programmable dividers and multipliers within the PLL stages, rather than requiring separate external frequency synthesis components. This integration reduces the need for external components, simplifying the circuit and reducing cost while maintaining frequency accuracy.
Solution Approach 2:
The patent designs the PLL circuit with programmable dividers and multipliers that can be configured for different frequency synthesis requirements. This multi-functionality allows the same circuit to achieve various frequency multiplication ratios without requiring different hardware configurations, reducing component complexity and cost while maintaining the ability to achieve accurate frequency generation.
Data Source
AI summary
A signal generator circuit includes an oscillator operative to generate a first signal having a first frequency associated therewith, and a phase stepper circuit coupled to the oscillator. The phase stepper circuit is configured to receive a plurality of control signals indicative of respective phases of the first signal, and to generate a second signal as a function of the plurality of control signals. The second signal has a second frequency associated therewith that is a fractional multiple or a fractional division of the first frequency. The second signal has a phase associated therewith which changes with periods of the second signal.