Digital Ring Oscillator Clock Synchronization for Data Output Timing
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Solution Overview
Problem
Existing semiconductor devices, such as SDRAM and SRAM, face challenges in synchronizing data output signals with an input clock signal efficiently, as prior methods like Delay Locked Loops (DLL) and Phase Locked Loops (PLL) consume excessive power and require many cycles to synchronize, and often mix digital and analog circuits, which is undesirable.
Innovation Solution
A digital ring oscillator is used to synchronize output signals with an input clock signal, employing a gated ring oscillator that can be turned on and off without delay, using digital methods to generate phase-aligned clock signals, and adjusting frequencies through circuit delays based on signal duration measurements, eliminating the need for Voltage-Controlled Oscillators or Delay-Locked Loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Delay Locked Loop (DLL) or Phase Locked Loop (PLL) methods are used to synchronize output signals with input clock, then phase alignment is achieved, but power consumption increases excessively
Solution Approach 1:
The patent replaces analog synchronization mechanisms (DLL/PLL) with a fully digital synchronization circuit. The digital circuit uses digital delay elements and digital signal processing to achieve phase alignment, eliminating the need for analog voltage-controlled oscillators and reducing power consumption while maintaining synchronization reliability
Solution Approach 2:
The patent changes the operating parameters by using digital delay control instead of analog voltage control. The synchronization is achieved by adjusting digital delay values through logic circuits rather than analog voltage adjustments, which reduces power consumption while maintaining phase alignment capability
2Reliability
If DLL or PLL methods are used for synchronization, then phase alignment is achieved, but many cycles are required to synchronize
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing optimal delay values in lookup tables before synchronization is needed. When synchronization is required, the circuit quickly retrieves pre-computed delay values rather than iterating through multiple cycles to find the correct delay, significantly reducing synchronization time while maintaining phase alignment accuracy
3Reliability
If analog circuits are mixed with digital circuits in the same manufacturing process, then synchronization functionality is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent applies homogeneity by making the entire synchronization circuit digital, using only digital logic elements that can be manufactured using standard digital CMOS processes. This eliminates the need to mix analog and digital circuits in the same manufacturing process, simplifying fabrication while maintaining full synchronization functionality through digital delay and phase detection circuits
Data Source
AI summary
A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period Πn of 1/(f1*2n), wherein f1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal, so a multiple of the clock frequency is produced. A number of delayed signals are generated, each having the same period as the input clock signal, but delayed by multiples of one-half the oscillator period from the input clock. The phase difference between the unadjusted output signal each delayed signal is determined, and the smallest value of the phase difference calculated. This smallest phase difference value is then added to the clock signal, resulting in a delayed clock, which is then used to generated the delayed output signal, which will be in close synchronization with the input clock.