Current Mirror Over Voltage Stress Testing Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing current mirror configurations face challenges in performing over voltage stress testing due to parasitic diodes activating a current path from the drain to the well, making it impossible to accurately measure gate current when the voltage on node Vgp is raised above Vdd.
Innovation Solution
A current mirror circuit with a switch between the drain and gate of a PMOS transistor, a clamp to limit voltage, and a bias source to control the switch's operation, ensuring it remains off during over voltage stress testing to prevent current paths and protect circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the voltage on node Vgp is raised above node Vdd to perform over voltage stress testing, then the gate current can be measured, but the parasitic diode from the drain to the well of device Mp2 is activated, providing a significant current path from node Vgp to source node Vdd
Solution Approach 1:
The patent extracts and removes the harmful parasitic current path by introducing a switch element that disconnects the drain-to-well parasitic diode during over-voltage stress testing. The switch is controlled to open the current path when Vgp exceeds Vdd, effectively taking out the harmful factor while allowing accurate gate current measurement.
Solution Approach 2:
The patent introduces a switch as an intermediary element between the drain and gate of Mp2, controlled by a bias source. This intermediary prevents the direct current path through the parasitic diode while still allowing the gate voltage to be raised for stress testing, mediating between the testing requirement and the harmful current path.
2Reliability
If components connected to the gate node are designed to withstand high DC voltage, then over voltage stress testing can be performed, but all components must not provide any current paths from the node
Solution Approach 1:
The patent applies dynamics by making the switch element controllable and changeable between ON and OFF states. During normal operation, the switch is ON to maintain current mirror functionality. During over-voltage stress testing, the switch is OFF to block current paths. This dynamic behavior allows the system to adapt to different operating conditions and prevent harmful current leakage.
Solution Approach 2:
The bias source is configured to preemptively turn off the switch before the parasitic diode can become forward-biased and conduct current. By anticipating the over-voltage condition and activating the switch control in advance, the harmful current path is prevented before it can occur.
Data Source
AI summary
A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first transistor; a bias source coupled to a control node of the switch such that the switch is ON during normal current mirror operation, and the switch is OFF during over voltage stress testing; and a clamp coupled between the control node of the switch and a source node.