Clock Divider Pulse Masking for Low-Noise Multi-Frequency Circuits
Solution Overview
Problem
In clock frequency divider circuits, the fluctuation in power consumption leads to increased power-supply noise and EMI noise due to simultaneous operation and shutdown of circuit blocks, which affects communication performance and power consumption.
Innovation Solution
A clock frequency divider circuit that masks clock pulses based on a frequency division ratio of N/S, using a mask control circuit to prioritize non-mask timings at communication timings and timings with no clock pulses in other circuits, ensuring consistent clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock frequency division is performed by masking clock pulses, then frequency division ratio can be adjusted, but power consumption fluctuates causing power-supply noise and EMI noise
Solution Approach 1:
The patent ensures continuous clock pulse generation by preventing simultaneous masking of clock pulses across different circuit blocks. The control mechanism monitors the operational states of multiple circuits and adjusts masking decisions to maintain at least one circuit in an operational state at any given time, thereby continuous current consumption and reducing power-supply noise and EMI noise
Solution Approach 2:
The patent dynamically changes the masking parameters based on the operational states of different circuit blocks. By monitoring whether circuits are in operation or shutdown states, the system adjusts which clock pulses to mask in real-time, optimizing frequency division while maintaining stable power consumption across varying operational conditions
2Adaptability or versatility
If clock pulses are masked to achieve frequency division, then different frequency clock signals can be generated, but communication between circuits becomes complex requiring special timing designs
Solution Approach 1:
The patent applies uniform masking control logic across all circuit blocks that require frequency division. By using the same control mechanism and masking strategy for different circuits, the system achieves homogeneous frequency division behavior, simplifying communication timing design while still allowing different operational frequencies across circuit blocks
3Adaptability or versatility
If multiple circuits operate at different frequencies, then functional flexibility is improved, but power consumption instability increases
Solution Approach 1:
The patent maintains continuous and stable power consumption by ensuring that when some circuits are in shutdown state with clock pulses masked, other circuits remain in operational state with clock pulses active. This continuous operation across different circuits at different frequencies stabilizes overall power consumption while preserving functional flexibility
Data Source
AI summary
A clock frequency divider circuit 11 according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by masking (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency divider circuit 11 includes a mask control circuit that generates a mask signal in which a non-mask timing is preferentially assigned to a clock pulse at a timing at which no clock pulse exists in a clock signal used in a circuit Ai other than a target circuit Bi using the output clock signal among S clock pulses of the input clock signal, and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.