Programmable Duty-Cycle Clock Generator With Low Jitter
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Solution Overview
Problem
Modern electronic circuit designs require clock signals with specific, well-defined duty cycles, but existing techniques lack simplicity and efficiency in programming clock frequency and duty cycle while maintaining low jitter and phase noise.
Innovation Solution
The solution involves a signal generator apparatus comprising counters and a toggle latch that count oscillator signal cycles to produce an output signal with a predetermined duty cycle, allowing for easy programming of duty cycle and frequency by varying the cycle counts and using a toggle latch to transition states based on counter outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock signal generation techniques are used, then the circuit can operate, but the duty cycle precision and programming flexibility are insufficient
Solution Approach 1:
The clock signal generation is segmented into two independent counting processes: one counter counts a first number of cycles to generate the first transition signal, while another counter counts a second number of cycles to generate the second transition signal. This segmentation allows precise control of duty cycle by independently programming the two cycle counts, achieving high duty cycle precision without requiring a monolithic complex circuit.
Solution Approach 2:
The circuit employs programmable counters where the first number and second number of cycles can be dynamically configured through programming. This dynamic capability allows the duty cycle and clock frequency to be flexibly adjusted by changing the programmed values, providing both precision and adaptability without hardware redesign.
2Adaptability or versatility
If programmable clock generation is implemented, then frequency and duty cycle can be adjusted, but jitter and phase noise increase
Solution Approach 1:
The invention extracts the duty cycle control function from the frequency control function by using separate counting processes. The first counter handles the active high period counting while the second counter handles the full cycle counting, allowing independent optimization of each function and reducing the interference that causes jitter and phase noise in integrated programmable systems.
Solution Approach 2:
The patent introduces intermediate signals (first transition signal and second transition signal) that mediate between the oscillator output and the final clock signal. These intermediate signals serve as buffered control points that reduce direct interference in the timing-critical path, thereby maintaining signal stability while enabling programmability.
3Ease of manufacture
If simple counter-based generation is used, then the circuit is simple, but the duty cycle control precision is insufficient
Solution Approach 1:
Instead of using a single counter that must precisely divide the cycle, the invention uses two counters that count partial cycles (first number and second number). This partial counting approach, when combined, provides excessive precision in duty cycle control because the boundaries are defined by integer cycle counts rather than fractional divisions, maintaining simplicity while achieving high accuracy.
Data Source
AI summary
Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.