DLL Frequency Multiplier with Dynamic Ratio and Low Jitter
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Solution Overview
Problem
Existing frequency multipliers for high-speed clock signals face challenges in reducing jitter, occupying large area, and high power consumption, with fixed frequency multiplication ratios, especially in DLL-based designs which struggle with dynamic frequency adjustment and high-speed operation.
Innovation Solution
A frequency multiplier design incorporating voltage regulators, input and output buffers, discharge and charge circuits, and a phase interpolator, along with an N to K multiplexer, to dynamically control the frequency multiplication ratio and minimize parasitic capacitance, enabling high-speed operation with reduced jitter and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL-based frequency multiplier is used to avoid jitter accumulation, then jitter characteristics are improved, but frequency multiplication capability deteriorates
Solution Approach 1:
The frequency multiplier is divided into multiple parallel paths (first path with first delay element and second path with second delay element) that process different phases of the input signal. Each path generates partial output signals that are combined to achieve the overall frequency multiplication effect, allowing the DLL to maintain its jitter-free operation while achieving frequency multiplication through constructive combination of multiple signal paths
Solution Approach 2:
Output signals from multiple parallel delay paths are merged together through addition or logical OR operations. The first output signal from the first delay path and the second output signal from the second delay path are combined to generate the final frequency-multiplied output, enabling frequency multiplication without the jitter accumulation problems of VCO-based approaches
2Adaptability or versatility
If a VCO-based PLL is used to achieve frequency multiplication, then frequency multiplication capability is improved, but jitter accumulation worsens
Solution Approach 1:
The patent replaces the mechanical/physical oscillation mechanism of a VCO with a digital logic-based delay line system. Instead of using a voltage-controlled oscillator that physically generates and accumulates phase errors, the invention uses combinatorial logic circuits and delay elements that deterministically generate frequency-multiplied signals without jitter accumulation, substituting a jitter-prone analog mechanism with a jitter-free digital mechanism
3Adaptability or versatility
If the number of delay elements is increased to achieve higher frequency multiplication ratio, then frequency multiplication capability is improved, but device area increases
Solution Approach 1:
The patent transitions from a single-dimensional sequential delay chain to a multi-dimensional parallel structure. By organizing delay elements in parallel paths (first path and second path with different phase shifts) and combining them through logical operations, the system achieves frequency multiplication ratios higher than the number of physical delay elements, effectively utilizing a higher dimensional signal space to reduce the area requirement
4Stability of the object's composition
If a first-order DLL system is used to maintain stability, then system stability is improved, but frequency multiplication precision deteriorates
Solution Approach 1:
The patent introduces feedback mechanisms including phase detectors that compare the frequency-multiplied output signal with the original input signal, and control logic that adjusts delay element settings based on phase error detection. This feedback loop compensates for manufacturing variations and timing skew in delay elements, maintaining both system stability and frequency multiplication precision simultaneously
Data Source
AI summary
A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.