Hybrid Reconfigurable Divider Circuits for Wide-Range Clock Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing divider circuits face challenges in maintaining high resolution while providing a large division factor range, especially when operating with high frequency input clock signals, making it difficult to achieve both high output resolution and a wide range of division factors.
Innovation Solution
The implementation of a dual-variable divider circuit topology using cascade-connected flip-flops and multiplexers, with different configurations for lower and upper range division factors, allows for variable length flip-flop chains and feedback circuits to support integer division, enabling high-frequency operation and high resolution in a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single variable divider circuit is used to provide a large division factor range, then the division factor range is increased, but the output resolution deteriorates
Solution Approach 1:
The patent divides the single variable divider circuit into two separate variable divider circuits: a first variable divider circuit for lower division factors (e.g., 1-7) and a second variable divider circuit for upper division factors (e.g., 8-15). Each circuit is optimized for its specific range, allowing the first circuit to maintain high resolution for small divisions while the second circuit handles larger divisions. This segmentation resolves the contradiction by preventing the resolution degradation that would occur in a single circuit attempting to cover the entire range.
Solution Approach 2:
The patent implements dynamic switching between the two variable divider circuits based on the required division factor. A control circuit determines which divider circuit to use based on the desired division factor, dynamically selecting the appropriate circuit to maintain optimal resolution. This dynamic adaptation allows the system to achieve high resolution for both lower and upper division factor ranges, resolving the contradiction between range and resolution.
2Measurement precision
If the divider circuit is designed for high resolution, then the output resolution is improved, but the circuit complexity increases
Solution Approach 1:
By segmenting the high-resolution requirement into two separate circuits, each handling a specific division factor range, the patent avoids the need for a single overly complex circuit. The first variable divider circuit uses fewer flip-flops and simpler logic for lower divisions, while the second uses an optimized structure for upper divisions. This segmentation reduces overall circuit complexity compared to a single circuit designed to handle all ranges with maximum resolution.
Solution Approach 2:
Each variable divider circuit is designed with local optimization for its specific division factor range. The first circuit uses a structure optimized for lower divisions with appropriate flip-flop configurations, while the second circuit uses structures optimized for upper divisions. This local quality approach ensures high resolution in each segment without requiring the entire system to be over-engineered, thereby reducing overall complexity while maintaining high resolution performance.
3Speed
If a variable divider circuit operates at high frequency, then the input clock frequency is increased, but maintaining high resolution becomes difficult
Solution Approach 1:
The patent segments the high-frequency operation into two separate circuits, each optimized for their respective division factor ranges. The first variable divider circuit uses a structure with fewer logic stages and flip-flops, allowing it to operate at high frequencies for lower divisions without resolution loss. The second circuit uses an optimized structure for upper divisions that also maintains high-frequency capability. This segmentation allows both circuits to achieve high-frequency operation while maintaining resolution, as each circuit's simpler structure within its range reduces timing constraints.
Data Source
AI summary
An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.