Dual-Modulus Fractional Frequency Divider With Half-Clock Resolution
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Solution Overview
Problem
Conventional dual-modulus integer frequency dividers are insufficient for modern complex communication systems, requiring a novel dual-modulus divide-by-N/(N+0.5) frequency divider capable of performing both integer and fractional frequency divisions, with the ability to dynamically change the value of N for adaptable frequency synthesizers.
Innovation Solution
A dual-modulus frequency divider design utilizing two pairs of edge-triggered flip-flops, a frequency-dividing selector, and a modulus logic circuit to select between N and N+0.5 frequency-dividing modes, along with a switching-control circuit to dynamically switch between integer and fractional divisions, achieving division resolution of half the input clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional dual-modulus integer frequency dividers are used, then the circuit structure is simple, but the adaptability for modern complex communication systems is insufficient
Solution Approach 1:
The patent implements dynamic switching between integer division mode (divide-by-N) and fractional division mode (divide-by-N+0.5) through a mode selection signal. The circuit uses edge-triggered flip-flops and control logic that can dynamically adjust the division ratio based on system requirements, enabling adaptation to different communication standards and frequency synthesizer configurations without requiring multiple dedicated circuits
Solution Approach 2:
The frequency divider circuit is designed to perform multiple functions: it can operate as an integer frequency divider (divide-by-N) or a fractional frequency divider (divide-by-N+0.5) within the same circuit structure. This multi-functionality is achieved through the dual-mode operation capability, allowing a single circuit to replace what would traditionally require separate integer and fractional division circuits, thereby improving adaptability while managing complexity
2Object-generated harmful factors
If conventional integer frequency division is used, then the circuit is simple, but the quantization noise power is high
Solution Approach 1:
The patent changes the division ratio parameter from integer values (N) to fractional values (N+0.5) to reduce quantization noise. By introducing half-integer division ratios through the fractional mode operation, the system achieves finer frequency resolution and reduced quantization effects compared to conventional integer division, thereby lowering quantization noise power while maintaining circuit feasibility
3Object-generated harmful factors
If fractional frequency dividers are implemented to reduce quantization noise, then the quantization noise power decreases, but the circuit becomes complicated and area-consuming
Solution Approach 1:
The patent employs dynamic mode switching between integer and fractional division using control signals that activate different operational paths within the same circuit. The edge-triggered flip-flops and control logic dynamically adjust the division behavior based on the desired mode, avoiding the need for separate dedicated fractional division circuits and thereby reducing overall circuit complexity and area
Solution Approach 2:
The circuit is designed as a universal frequency divider that can perform both integer (divide-by-N) and fractional (divide-by-N+0.5) division functions within a single unified structure. This multi-functionality eliminates the need for separate integer and fractional division circuits, significantly reducing circuit area and complexity while still achieving the noise reduction benefits of fractional division when needed
Data Source
AI summary
A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock.