Clock Duty Cycle Measurement Using Divider Failure Frequency
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Solution Overview
Problem
Conventional methods for measuring small changes in the duty cycle of digital signals, particularly at high frequencies in the GHz range, are either expensive or destructive, and existing solutions are not effective in accurately determining incremental adjustments in the picosecond range.
Innovation Solution
A method and apparatus that utilize a clock signal generator, a variable duty cycle circuit, and a divider circuit to determine duty cycle information by sweeping the frequency of the clock signal and observing the failure point of the divider circuit, allowing for precise measurement of incremental changes in duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high speed oscilloscope with very large bandwidth is used to measure duty cycle changes in the picosecond range, then measurement precision is improved, but cost and device complexity increase significantly
Solution Approach 1:
The patent introduces a divider circuit as an intermediary component between the clock signal source and the measurement system. This divider circuit fails at a known maximum frequency that corresponds to the duty cycle measurement, allowing the use of lower-cost, lower-bandwidth oscilloscopes to indirectly measure picosecond-range duty cycle changes through frequency domain transformation rather than direct time domain measurement
Solution Approach 2:
The invention transforms the measurement parameter from direct time domain duty cycle measurement to frequency domain measurement by utilizing the divider circuit's failure frequency characteristic. By sweeping the clock frequency and identifying the point where the divider circuit fails, the system converts a difficult time domain measurement into a more accessible frequency domain measurement that can be performed with less expensive equipment
2Measurement precision
If picosecond imaging circuit analysis (PICA) is used to measure duty cycle, then measurement precision is improved, but the component under test is destroyed
Solution Approach 1:
The patent creates a functional copy of the measurement approach by using a separate divider circuit that replicates the timing characteristics of the clock signal without requiring direct observation of the original signal's leading and trailing edges. This allows duty cycle measurement through the divider's failure frequency rather than through destructive photon detection of the actual clock signal
3Ease of operation
If conventional measurement methods are used for low frequency signals, then ease of operation is maintained, but measurement precision deteriorates for high frequency signals in the GHz range
Solution Approach 1:
The patent creates a universal measurement system that can handle both low frequency signals (maintaining ease of operation) and high frequency GHz range signals (achieving picosecond precision). The divider circuit approach works across a wide frequency range, allowing the same measurement methodology to be applied regardless of the input signal frequency, thus providing multi-functionality that bridges the gap between simple conventional methods and precision high-speed measurement requirements
Data Source
AI summary
The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.