Clock Divider Latch Switching for 50% Duty Ratio at Odd Division
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Solution Overview
Problem
Clock divider circuits in semiconductor devices face challenges in maintaining a 50% duty ratio for output clock signals when the division number is odd, as existing designs often fail to achieve this due to the cyclic coupling of latch circuits and clock switch configurations.
Innovation Solution
The clock divider circuit employs a configuration where latch circuits are cyclically coupled and latch clock signals are interchanged in the second group of latch circuits when the division number is odd, ensuring that the duty ratio remains at 50% by adjusting the trigger signals and clock switch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If latch circuits are cyclically coupled with standard clock switch configuration, then the circuit structure is simple, but the duty ratio cannot be maintained at 50% when division number is odd
Solution Approach 1:
The patent applies asymmetry by differentiating the clock switch configuration between even and odd division modes. Specifically, when the division number is odd, the clock switches are configured to interchange latch clock signals between different groups of latch circuits, creating an asymmetric signal distribution pattern that balances the duty ratio. This asymmetric configuration allows the circuit to achieve 50% duty ratio for odd divisions without requiring complete structural redesign.
Solution Approach 2:
The patent implements dynamics by making the clock switch configuration adaptive based on the division number. The circuit dynamically adjusts its operation mode: for even division numbers, it uses standard cyclic coupling; for odd division numbers, it switches to a modified mode where latch clock signals are interchanged between groups. This dynamic adaptation allows the same circuit structure to maintain 50% duty ratio across both even and odd division cases.
2Measurement precision
If the circuit uses a unified configuration for even and odd division, then the device complexity is low, but the timing precision deteriorates for odd division
Solution Approach 1:
The patent applies local quality by applying different clock signal distribution strategies to different groups of latch circuits based on the division number. When division is odd, the circuit selectively interchanges latch clock signals between specific groups rather than uniformly across all latches. This localized differentiation ensures precise timing control for odd divisions while maintaining overall circuit simplicity.
3Manufacturing precision
If latch clock signals are interchanged for odd division, then the duty ratio is maintained at 50%, but the circuit configuration becomes more complex
Solution Approach 1:
The patent achieves universality by designing the clock switch network to perform multiple functions: it operates in standard mode for even divisions and automatically switches to signal interchange mode for odd divisions. The same clock switch infrastructure handles both operational modes, eliminating the need for separate dedicated circuits for each case. This multi-functional design maintains ease of operation while achieving 50% duty ratio for all division numbers.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.