Counting Chain Pulse Counters Using Semiconductor Devices TRIZ Cases
- Counting Control Circuit for ECS Timing in Semiconductor Memory
An independent counting clock decouples ECS from refresh commands, helping semiconductor memory finish error scrub on time with lower power.
- Clock Divider Latch Switching for 50% Duty at Odd Division
Interchanging latch clock signals in one latch group keeps divided clocks at 50% duty even for odd division ratios.
- Differential Signal Converter With Stable Zero-Crossing Paths
A multiply-then-divide converter creates balanced differential outputs from a single-ended signal to improve TDC linearity and zero-crossing stability.
- Clock Divider Latch Switching for 50% Duty Ratio at Odd Division
Interchanged latch clock signals let a cyclic clock divider keep a 50% duty ratio even when the division number is odd.
- Clock Step Control Circuit for Overcurrent Frequency Switching
During overcurrent events, the circuit switches among divided clock frequencies to avoid shutdown, protect the chip, and preserve computing power.
- Semiconductor Memory Clock Leveling for Signal Skew Synchronization
Internal clock leveling uses feedback between system and data clocks to compensate signal skew in daisy-chained semiconductor memories.
- Semiconductor Memory Clock Leveling for Signal Skew Compensation
Clock leveling feedback aligns system and data clocks in serial semiconductor memories to compensate skew and stabilize data transfer.
- Programmable Synchronous Clock Divider for Duty Cycle Stability
Programmable duty cycle control in a synchronous clock divider compensates aging and chip variation to keep divided clocks stable.
- Multi-Phase Clock Divider Circuit With Low-Area Frequency Division
A counter and phase-aligned flip-flops divide multi-phase clock inputs while preserving phase offsets and reducing clock generator area.