Multi-Phase Clock Divider Circuit With Low-Area Frequency Division
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Solution Overview
Problem
Existing clock divider circuits require significant integrated circuit surface area and complexity to generate multiple clock frequencies, especially when dividing multi-phase clock signals, leading to increased complexity and area usage.
Innovation Solution
A clock divider circuit that receives multiple input clock signals of the same frequency, with each signal having a phase offset, and uses a counter and flip-flops to divide the frequency by an integer factor, while maintaining minimal circuit complexity and area usage, by employing a method where each flip-flop receives an input clock signal and a count signal or clock output signal from another flip-flop, generating output signals with specific phase offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock generators are used for various required clock frequencies, then each clock signal can be generated independently, but the area and complexity of the clock generator module increases
Solution Approach 1:
A single clock generator module generates multiple clock frequencies by combining one phase generator with multiple phase shifters. Each phase shifter receives the same input clock signal and produces a phase-shifted version, allowing the system to provide multiple independent clock signals from a single generator, thereby reducing overall complexity while maintaining independent generation capability.
Solution Approach 2:
The clock generation function is segmented into separate modular components: a central phase generator and multiple independent phase shifters. This segmentation allows each component to be optimized independently and enables flexible configuration of clock frequencies and phases, reducing the complexity of the overall system while maintaining reliability.
2Area of stationary object
If a single clock generator provides the highest frequency clock signal, then the clock generator module area is reduced, but the complexity of generating lower frequency clock signals increases
Solution Approach 1:
The phase shifters utilize periodic switching based on the input clock signal to generate phase-shifted versions. By periodically selecting different phases of the input clock signal through controlled switching, the system generates multiple frequency outputs from a single high-frequency source without requiring additional complex frequency synthesis circuits, thereby maintaining low area and complexity.
Solution Approach 2:
Phase shifters act as intermediary components between the single high-frequency clock generator and the multiple required clock outputs. These intermediaries transform the single input clock signal into multiple phase-shifted signals through controlled delay and switching, simplifying the overall architecture while enabling flexible frequency and phase control.
3Productivity
If traditional clock dividers are used to divide multi-phase clock signals, then frequency division can be achieved, but the integrated circuit surface area and circuit complexity increase significantly
Solution Approach 1:
The phase shifting and frequency division functions are merged into a single integrated structure where phase shifters directly process the input clock signal to produce both phase-shifted and frequency-divided outputs. This merging eliminates the need for separate divider circuits for each phase, significantly reducing circuit complexity and area while maintaining full frequency division capability across all phases.
Data Source
AI summary
A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2 π/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2 πK/m phase offset from the previous clock output signal.