Semiconductor Memory Clock Leveling for Signal Skew Synchronization
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Solution Overview
Problem
In electronic systems, semiconductor memories face challenges in synchronizing the timing of various signals, such as clocks, command, and address signals, due to signal skew when memories are coupled in series, which affects the performance and efficiency of memory operations.
Innovation Solution
The implementation of clock leveling operations within the semiconductor device, where the controller adjusts the timing of signals by providing feedback on the relative timing between system clocks and data clocks, allowing for compensation of signal skew through internal clock circuits and mode register programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memories are coupled in series to increase memory capacity, then the memory capacity is improved, but signal skew between clocks and data signals increases causing timing synchronization issues
Solution Approach 1:
The patent performs clock leveling operations before normal memory operations to pre-adjust the timing of clock signals. The controller initiates a clock leveling command that causes the memory device to adjust its internal clock timing relative to the data clock, compensating for skew caused by series coupling before actual data transfer begins.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device monitors the timing relationship between its internal clocks and the data clock, then adjusts its clock timing based on this feedback. The controller sends clock leveling commands and receives confirmation that timing adjustments have been made, creating a closed-loop system for timing synchronization.
2Manufacturing precision
If the timing of signals is adjusted to compensate for skew, then the timing synchronization is improved, but the complexity of signal timing control increases
Solution Approach 1:
The patent enables the memory device to automatically adjust its own clock timing through the clock leveling operation. The memory device independently monitors its timing relationships and performs self-correction by adjusting its internal clock phases, reducing the need for complex external timing control circuitry.
Solution Approach 2:
The patent uses existing memory control interfaces and clock circuits to perform multiple functions. The same command interface used for normal memory operations is also used to initiate clock leveling operations, and the existing clock distribution network is used both for data transfer timing and for the clock leveling adjustment process.
Data Source
AI summary
Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.