Semiconductor Memory Clock Leveling for Signal Skew Compensation
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Solution Overview
Problem
In electronic systems, semiconductor memories face challenges in synchronizing the timing of various signals, such as clocks, command, and address signals, due to signal skew when memories are coupled in series, which affects the proper operation and data transfer efficiency.
Innovation Solution
The implementation of clock leveling operations within the semiconductor device, where the controller adjusts the timing of signals by providing feedback on the relative timing between system clocks and data clocks, using complementary clocks and phase-controlled internal clocks to compensate for signal skew, allowing for synchronized memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memories are coupled in series to increase memory capacity, then the memory capacity is improved, but signal skew between clocks occurs which worsens timing synchronization
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures the relative timing between system clock and data clock signals, then communicates this timing information back to the controller. The controller uses this feedback to adjust the timing of signal transmission, thereby compensating for skew caused by series coupling and maintaining proper synchronization.
Solution Approach 2:
The patent dynamically adjusts timing parameters of clock signals based on measured skew. The memory device provides timing information that enables the controller to modify the phase or delay of clock signals, changing the timing parameters to compensate for the skew introduced by series coupling topology.
2Reliability
If signal timing is adjusted to compensate for skew, then timing synchronization is improved, but the complexity of the control system increases
Solution Approach 1:
The memory device performs self-measurement of clock timing skew and communicates the measured values back to the controller. This self-service approach allows the system to automatically detect and report timing issues without requiring complex external measurement equipment, simplifying the overall control architecture while maintaining synchronization accuracy.
Data Source
AI summary
Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.