Clock Step Control Circuit for Overcurrent Frequency Switching
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Solution Overview
Problem
Conventional overcurrent protection mechanisms in high-performance chips lead to system shutdown, performance loss, and potential chip damage due to excessive energy consumption, as they only reset the system to an idle state without effectively managing peak power demands.
Innovation Solution
A clock step control circuit and method that utilizes a clock divider, multiplexer, and controller to automatically reduce the clock frequency of the core clock signal when an overcurrent event occurs, selecting from multiple clock signals with different frequencies to maintain computing power and prevent system shutdown or chip damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating power of a chip is increased to meet peak performance requirements, then the computing power is improved, but the energy consumption exceeds the peak limit causing system shutdown or chip damage
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by switching between multiple clock signals with different frequencies based on workload demands. The controller monitors power consumption and dynamically selects appropriate clock frequencies, allowing the system to operate at high performance when needed while reducing power consumption during normal operation, thus resolving the contradiction between computing power and energy consumption
Solution Approach 2:
The patent changes the clock frequency parameter of the clock signal to control power consumption. By adjusting the clock frequency from high to low levels, the system can control the power consumption of the chip to stay within safe limits while maintaining acceptable computing performance, directly addressing the energy consumption issue
2Reliability
If a conventional overcurrent protection mechanism shuts down or resets the system, then the chip damage is prevented, but the performance loss and system complexity increase
Solution Approach 1:
Instead of static shutdown protection, the patent implements dynamic clock frequency adjustment as a protective measure. When overcurrent is detected, the controller gradually reduces clock frequency rather than immediately shutting down, allowing the system to maintain operation at reduced performance while still protecting against damage, thus resolving the contradiction between reliability and productivity
Solution Approach 2:
The patent employs feedback control where the controller continuously monitors power consumption and clock frequency, and adjusts the clock signal accordingly. When overcurrent conditions are detected, the feedback mechanism triggers clock frequency reduction to bring power consumption back within safe limits, providing protective feedback that maintains both chip safety and system operation
3Loss of energy
If the clock frequency is reduced to lower power consumption, then the energy consumption is controlled, but the computing power decreases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by switching between multiple clock signals with different frequencies based on workload demands. The controller monitors power consumption and dynamically selects appropriate clock frequencies, allowing the system to operate at high performance when needed while reducing power consumption during normal operation, thus resolving the contradiction between computing power and energy consumption
Solution Approach 2:
The patent changes the clock frequency parameter of the clock signal to control power consumption. By adjusting the clock frequency from high to low levels, the system can control the power consumption of the chip to stay within safe limits while maintaining acceptable computing performance, directly addressing the energy consumption issue
Data Source
AI summary
The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.