Counting Control Circuit for ECS Timing in Semiconductor Memory
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in completing Error Check and Scrub (ECS) operations within the required time frame due to reliance on refresh commands, leading to potential power consumption issues and incomplete error correction.
Innovation Solution
A counting control circuit is introduced, comprising a logic control circuit and a counting statistic circuit, which generates a counting clock signal independent of refresh commands, ensuring timely completion of ECS operations within 24 hours while reducing power consumption by controlling counting based on a logical relationship between the clock signal and identification signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECS operation is performed using refresh commands in related art, then memory error checking is achieved, but ECS operation cannot be completed within 24 hours and additional power consumption is generated
Solution Approach 1:
The patent segments the ECS operation from the refresh command sequence by introducing an independent counting control circuit. This circuit uses a separate clock signal and counter to track ECS operation completion, allowing ECS to be performed on a subset of memory rows rather than requiring all refresh commands to be dedicated to ECS. This segmentation enables ECS to be completed within the 24-hour window without compromising overall memory refresh requirements.
Solution Approach 2:
The patent introduces an intermediary counting control circuit that mediates between the refresh command generator and the ECS operation. This intermediary circuit monitors the counting clock signal, tracks the number of ECS operations performed, and generates identification signals to indicate when ECS completion criteria are met. This intermediary layer decouples the ECS timing from the refresh command timing, enabling independent optimization of both operations.
2Reliability
If ECS operation is performed using refresh commands in related art, then memory error checking is achieved, but additional power consumption is generated
Solution Approach 1:
The patent segments the memory system into refresh operation components and ECS operation components, each with independent control. By using a separate counting control circuit with its own clock signal and counter, the ECS operation can be performed on only the necessary portion of memory rows rather than requiring all refresh commands to be consumed by ECS. This reduces the total number of ECS operations needed and thereby reduces power consumption.
Solution Approach 2:
The patent changes the timing parameters of ECS operations by introducing a counting clock signal that is independent of the refresh command timing. The counting control circuit can accumulate ECS operations over time and generate identification signals when completion criteria are met, allowing ECS to be performed at optimized intervals rather than being constrained by refresh command timing. This parameter change enables more efficient power usage.
3Stability of the object's composition
If counting is performed based on refresh commands, then ECS timing is synchronized with refresh, but counting accuracy is affected when refresh commands are not executed
Solution Approach 1:
The patent introduces an intermediary counting control circuit that uses a separate counting clock signal independent of the refresh command timing. This intermediary counting mechanism accurately tracks the number of ECS operations performed without being affected by whether refresh commands are executed. The counter reliably increments based on the counting clock signal, providing precise measurement of ECS completion regardless of refresh command status.
Solution Approach 2:
The patent segments the timing control into two independent parts: refresh command timing and ECS operation timing. The counting control circuit uses its own clock signal and counter separate from the refresh command generator, allowing accurate counting of ECS operations without being coupled to refresh command execution. This segmentation eliminates the interference between refresh timing variations and ECS counting accuracy.
Data Source
AI summary
A counting control circuit includes a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit. The logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal. The counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal which indicates a generation of a command signal for performing a first operation, here, the first identification signal is in a valid state when a counting value meets a preset condition.