Clock Divider Phase Alignment Without Root Clock Restart
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Solution Overview
Problem
Existing clock chips require restarting the root clock or entire system to realign clock channels upon component restart, causing downtime.
Innovation Solution
A tri-statable signal line connects each clock channel to every other channel, allowing any channel clock to serve as a reference for alignment, with divider timing synchronization circuitry adjusting the channel dividers to align with the reference signal without disturbing the root clock or other channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the root clock or entire system is restarted to realign clock channels, then clock synchronization is restored, but system downtime increases
Solution Approach 1:
The patent segments the clock channel alignment problem into individual channel operations rather than requiring system-wide restart. Each clock channel can be independently realigned using the tri-statable signal line to transmit reference signals selectively to specific channels, allowing granular control and avoiding unnecessary system downtime.
Solution Approach 2:
The tri-statable signal line acts as an intermediary mechanism that enables clock channel realignment without requiring root clock interruption. This intermediate structure allows reference signals to be transmitted selectively between clock channels, facilitating alignment while maintaining continuous operation of the root clock and other channels.
2Manufacturing precision
If the root clock is stopped to realign clock channels, then phase synchronization is achieved, but operational continuity is disrupted
Solution Approach 1:
The patent implements preliminary action by capturing and storing reference clock signals in latches before alignment operations. The divider timing synchronization circuitry uses these pre-captured references to adjust divider ratios and phase relationships, ensuring precise synchronization is achieved without interrupting the root clock operation or other channel functionality.
Solution Approach 2:
The system dynamically adjusts divider ratios and phase relationships in real-time using the divider timing synchronization circuitry. This dynamic control allows clock channels to be realigned on-the-fly without static system restart, maintaining operational continuity while achieving the required phase synchronization precision.
3Productivity
If clock channels are realigned without stopping the root clock, then system availability is maintained, but alignment complexity increases
Solution Approach 1:
The patent implements self-service through automatic phase and frequency detection circuits that autonomously measure and adjust clock channel parameters. The divider timing synchronization circuitry automatically compares reference signals with channel outputs and adjusts divider ratios without requiring complex external control, reducing alignment complexity while maintaining system availability.
Solution Approach 2:
The system uses feedback mechanisms where the divider timing synchronization circuitry continuously monitors phase and frequency relationships between reference signals and clock channel outputs. This feedback drives automatic adjustments to divider ratios and timing, simplifying the alignment process while maintaining precision and system availability simultaneously.
Data Source
AI summary
In an example, a system includes one or more clock channels on a clock chip, each clock channel configured to provide a clock signal. The system also includes a signal line coupled to the one or more clock channels, the signal line configured to send clock signals to and receive clock signals from each clock channel. The system includes a controller configured to select a first clock signal from a first clock channel to drive the signal line. The system also includes divider timing synchronization circuitry in a second clock channel configured to align a second clock signal from the second clock channel with the first clock signal.