Clock Divider Circuit for Predictable DLL Phase Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock divider circuits in delay-locked loops (DLLs) face challenges in determining predictable phase relationships between delayed and reference clocks, leading to prolonged lock scenarios as they operate at higher frequencies.
Innovation Solution
A clock divider circuit is designed with a first and second divider circuit to generate complementary intermediate clocks, and a third circuit selects one of these clocks based on phase relationships to provide a stable output clock, incorporating a delay circuit and phase detector to synchronize the clocks efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock divider circuits are used in DLLs to operate at higher frequencies, then the operating speed increases, but the phase relationship between delayed and reference clocks becomes unpredictable leading to longer lock scenarios
Solution Approach 1:
The clock divider circuit is segmented into multiple independent divider circuits (first divider circuit, second divider circuit, third divider circuit) that operate in parallel. Each divider circuit processes clock signals independently and generates intermediate clocks with predictable phase relationships. This segmentation allows the system to maintain higher operating speeds while ensuring predictable phase detection, thereby reducing lock scenario duration.
Solution Approach 2:
Intermediate clocks are introduced as intermediary signals between the reference clock and the delayed clock. These intermediate clocks are generated by divider circuits with known phase relationships, serving as mediators that facilitate accurate phase detection. The phase detector compares the phase of intermediate clocks rather than directly comparing delayed and reference clocks, enabling predictable phase relationship determination even at higher frequencies.
2Productivity
If clock frequency is increased to operate electronic devices at higher speeds, then productivity increases, but the ability of DLL circuits to determine phase relationship deteriorates
Solution Approach 1:
The divider circuits perform preliminary division of the reference clock to generate intermediate clocks with predetermined phase relationships before the phase detection process. This preliminary action ensures that when phase detection occurs at higher frequencies, the phase relationship between signals is already established and predictable, making detection easier despite the increased operating frequency.
Solution Approach 2:
The patent replaces direct phase comparison between delayed and reference clocks with a substituted mechanism involving intermediate clocks. Instead of mechanically comparing high-frequency signals directly, the system uses divider circuits to create intermediate representations with known phase relationships, substituting a more manageable comparison process that works reliably at higher frequencies.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.