Clock Divider State Control for Low-Level Retention Transitions
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Solution Overview
Problem
Existing clock dividers in SoC systems fail to ensure that the output clock is in a low level state during retention signal transition periods, leading to improper retention operations and restricted clock design freedom.
Innovation Solution
A clock divider system with a state machine that controls the counter to maintain the output clock in a low level state during retention signal transitions, ensuring proper retention operations and allowing for flexible divide value changes without deteriorating clock duty quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock gating is performed in a clock divider equipped with a counter, then clock toggle can be stopped, but the output clock may stop at a high level instead of a low level depending on the count state of the counter
Solution Approach 1:
The state machine detects the retention signal transition beforehand and controls the counter to reach a predetermined count value (where output clock is low) before the retention operation starts. This preliminary control ensures the output clock is in the required low level state when retention begins, regardless of the counter's current state.
Solution Approach 2:
The counter operation is made dynamic by selectively controlling it based on the retention signal state. During retention signal transition periods, the counter operation is controlled to ensure low level output; during normal operation, the counter operates freely to generate divided clocks. This dynamic control resolves the contradiction between reliability and design freedom.
2Reliability
If the counter operation is controlled to ensure low level output during retention, then retention operation can be performed properly, but the clock design flexibility is restricted
Solution Approach 1:
The counter operation is made dynamic by selectively controlling it based on the retention signal state. During retention signal transition periods, the counter operation is controlled to ensure low level output; during normal operation, the counter operates freely to generate divided clocks. This dynamic control resolves the contradiction between reliability and design freedom.
Solution Approach 2:
The control mechanism applies quality control only locally during retention signal transition periods rather than globally. The state machine intervenes specifically when the retention signal transitions, controlling the counter to ensure low level output only during these critical moments, while allowing full clock design flexibility during normal operation.
3Reliability
If the output clock is forced to low level during retention signal transition, then retention can be performed properly, but the clock duty ratio may be affected
Solution Approach 1:
The state machine detects the retention signal transition beforehand and controls the counter to reach a predetermined count value (where output clock is low) before the retention operation starts. This preliminary control ensures the output clock is in the required low level state when retention begins, regardless of the counter's current state.
Solution Approach 2:
During retention signal transition periods, the system skips normal counter operation and directly controls the output to maintain low level. This temporary deviation from normal operation ensures retention reliability without permanently affecting the clock duty ratio, as normal operation resumes after the transition period.
Data Source
AI summary
Disclosed are a clock divider and a method of controlling the same to ensure that an output clock of the clock divider is in a low level state during a retention signal transition period such that a retention operation can be performed smoothly. The clock divider includes a counter configured to count an input clock and generate a counter output for dividing the input clock, an output clock generator configured to generate clock edges according to the counter output and generate an output clock divided from the input clock, and a state machine configured to control the counter such that the output clock is in a low level during a retention signal transition period according to a clock low request from a power management unit.