Clock Divider Synchronization Using Slip Cycles and Shared PLLs
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Solution Overview
Problem
Existing clock synchronization methods in electronic devices face challenges in achieving precise frequency division and synchronization of multiple clock dividers, particularly in systems-on-chip (SoCs), leading to increased area and power consumption, and difficulties in meeting frequency resolution, range, and low-jitter requirements.
Innovation Solution
The use of fractional frequency dividers that provide programmable, low-jitter clock signals with fine frequency resolution, utilizing quadrature frequency dividers and error correction systems to synchronize sub-rate clocks, reducing the need for multiple PLL cores and minimizing silicon area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple PLL cores are used to achieve precise frequency division and synchronization, then frequency resolution and low-jitter requirements are met, but silicon area and power consumption increase
Solution Approach 1:
The patent merges multiple PLL cores into a single PLL core that shares resources across multiple clock domains. Instead of having separate PLLs for each clock divider, one PLL core generates a high-frequency clock that is then distributed to multiple fractional frequency dividers, reducing the overall silicon area while maintaining frequency precision through shared phase-locked loop architecture
Solution Approach 2:
The single PLL core is designed to serve multiple functions by generating a master high-frequency clock signal that feeds multiple fractional frequency dividers. This universal clock source can be divided into different frequencies for various clock domains within the SoC, eliminating the need for dedicated PLLs in each domain while maintaining synchronization and frequency resolution
2Measurement precision
If multiple PLL cores are used to achieve precise frequency division and synchronization, then frequency resolution and low-jitter requirements are met, but power consumption increases
Solution Approach 1:
The patent combines multiple power-consuming PLL cores into a single shared PLL core. By consolidating the phase-locked loop functionality into one core that serves multiple clock domains, the overall power consumption is reduced while maintaining the ability to generate precise frequency divisions through fractional frequency dividers that operate from the shared clock source
3Reliability
If conventional clock synchronization methods are used, then clock signals are generated, but synchronization precision and jitter performance are insufficient
Solution Approach 1:
The patent implements feedback mechanisms within the fractional frequency dividers that use phase information from the shared PLL core to adjust and synchronize output clock signals. This feedback ensures that all clock domains remain synchronized to the master clock while maintaining low jitter through phase-correction algorithms that compensate for timing variations across different frequency divisions
Data Source
AI summary
Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.