Clock-Domain Interrupt Synchronization Using Edge Pulse Conversion
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Solution Overview
Problem
Signal transmission between different clock domains often results in multiple synchronized interrupt signals or failure to generate a synchronized signal, leading to repeated or missed interrupt operations, due to the inefficiencies of existing synchronizer circuits.
Innovation Solution
A signal transmitting circuit comprising an edge detection circuit and a pulse synchronization circuit, which converts the initial interrupt signal into a single pulse signal and synchronizes it with the slower clock domain, ensuring only one trigger interrupt signal is generated, comprising edge detection, flip, synchronization, and edge extraction circuits operating across different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronizer circuit is used to transmit interrupt signals from a faster clock domain to a slower clock domain, then signal synchronization is achieved, but multiple synchronized interrupt signals may be generated or no signal may be output, leading to repeated or missed interrupt operations
Solution Approach 1:
The synchronizer circuit is divided into multiple independent flip-flops (first flip-flop, second flip-flop, third flip-flop) that process different aspects of the interrupt signal separately. Each flip-flop is clocked by the slower clock signal and samples the signal at different stages, ensuring that only one synchronized interrupt signal is generated even when the input signal remains high for multiple clock cycles.
Solution Approach 2:
The first flip-flop samples the interrupt signal in advance and generates an intermediate signal that is then processed by subsequent flip-flops. This preliminary action ensures that the signal is stabilized before further processing, preventing multiple output pulses and ensuring reliable single-signal generation.
2Adaptability or versatility
If existing synchronizer circuits are used for signal transmission between different clock domains, then clock domain crossing is enabled, but the circuit may fail to output a synchronized interrupt signal, causing missed interrupt operations
Solution Approach 1:
Each flip-flop in the synchronizer circuit is specifically designed with a particular function: the first flip-flop captures the initial edge of the interrupt signal, the second flip-flop processes the intermediate state, and the third flip-flop generates the final synchronized output. This localized functional differentiation ensures that the circuit reliably generates a single synchronized interrupt signal across different clock domains.
Solution Approach 2:
The output of each flip-flop is fed back as the input to the next flip-flop, creating a feedback chain that processes the interrupt signal through multiple stages. This feedback mechanism ensures that the signal is properly synchronized and that only one interrupt signal is generated, preventing both missed and repeated operations.
Data Source
AI summary
A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed.